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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_stream_integer_type.v36 logic [127:0] packed_data_128; register
120 packed_data_128 = {<<32{int_in}};
130 {<<32{int_out}} = packed_data_128;
152 packed_data_128 = {<<int{int_in}};
162 {<<int{int_out}} = packed_data_128;
177 packed_data_128 = 0;
189 $display("TEST: packed_data_128=%0h", packed_data_128);
210 … $display("packed_data_128=%0h, packed_data_128_ref=%0h ", packed_data_128, packed_data_128_ref);
247 …$display(" %s packed_data_128=%0h,packed_data_128_ref=%0h ",name, packed_data_128, packed_data_128…
292 packed_data_128 = 0;
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H A Dt_stream_integer_type.out13 120 | packed_data_128 = {<<32{int_in}};
47 …r ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 12…
49 130 | {<<32{int_out}} = packed_data_128;
93 152 | packed_data_128 = {<<int{int_in}};
97 152 | packed_data_128 = {<<int{int_in}};