Home
last modified time | relevance | path

Searched refs:packed_data_128_i (Results 1 – 2 of 2) sorted by relevance

/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_stream_integer_type.v42 logic [127:0] packed_data_128_i; register
121 packed_data_128_i = {<<32{integer_in}};
131 {<<32{integer_out}} = packed_data_128_i;
153 packed_data_128_i = {<<integer{integer_in}};
163 {<<integer{integer_out}} = packed_data_128_i;
181 packed_data_128_i = 0;
190 $display("TEST: packed_data_128_i=%0h", packed_data_128_i);
214 …$display("packed_data_128_i=%0h, packed_data_128_i_ref=%0h", packed_data_128_i, packed_data_128_i_…
250 …$display(" %s packed_data_128_i=%0h,packed_data_128_i_ref=%0h", name, packed_data_128_i, packed_da…
293 packed_data_128_i = 0;
[all …]
H A Dt_stream_integer_type.out17 121 | packed_data_128_i = {<<32{integer_in}};
51 … ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 1…
53 131 | {<<32{integer_out}} = packed_data_128_i;
101 153 | packed_data_128_i = {<<integer{integer_in}};
105 153 | packed_data_128_i = {<<integer{integer_in}};