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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_stream_integer_type.v45 logic [255:0] packed_data_256; register
122 packed_data_256 = {<<64{longint_in}};
132 {<<64{longint_out}} = packed_data_256;
154 packed_data_256 = {<<longint{longint_in}};
164 {<<longint{longint_out}} = packed_data_256;
182 packed_data_256 = 0;
191 $display("TEST: packed_data_256=%0h", packed_data_256);
218 … $display("packed_data_256=%0h, packed_data_256_ref=%0h ", packed_data_256, packed_data_256_ref);
253 …$display(" %s packed_data_256=%0h, packed_data_256_ref=%0h ", name, packed_data_256, packed_data_2…
294 packed_data_256 = 0;
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H A Dt_stream_integer_type.out21 122 | packed_data_256 = {<<64{longint_in}};
55 …r ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 25…
57 132 | {<<64{longint_out}} = packed_data_256;
109 154 | packed_data_256 = {<<longint{longint_in}};
113 154 | packed_data_256 = {<<longint{longint_in}};