Home
last modified time | relevance | path

Searched refs:packed_data_64 (Results 1 – 2 of 2) sorted by relevance

/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_stream_integer_type.v30 logic [63:0] packed_data_64; register
119 packed_data_64 = {<<16{shortint_in}};
129 {<<16{shortint_out}} = packed_data_64;
151 packed_data_64 = {<<shortint{shortint_in}};
161 {<<shortint{shortint_out}} = packed_data_64;
176 packed_data_64 = 0;
188 $display("TEST: packed_data_64=%0h", packed_data_64);
206 $display("packed_data_64=%0h, packed_data_64_ref=%0h", packed_data_64, packed_data_64_ref);
244 …$display(" %s packed_data_64=%0h,packed_data_64_ref=%0h", name, packed_data_64, packed_data_64_ref…
291 packed_data_64 = 0;
[all …]
H A Dt_stream_integer_type.out9 119 | packed_data_64 = {<<16{shortint_in}};
43 …r ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 …
45 129 | {<<16{shortint_out}} = packed_data_64;
85 151 | packed_data_64 = {<<shortint{shortint_in}};
89 151 | packed_data_64 = {<<shortint{shortint_in}};