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Searched refs:packed_time_256 (Results 1 – 2 of 2) sorted by relevance

/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_stream_integer_type.v48 logic [255:0] packed_time_256; register
123 packed_time_256 = {<<64{time_in}};
133 {<<64{time_out}} = packed_time_256;
155 packed_time_256 = {<<time{time_in}};
165 {<<time{time_out}} = packed_time_256;
183 packed_time_256 = 0;
192 $display("TEST: packed_time_256=%0h", packed_time_256);
222 $display("packed_time_256=%0h, packed_time_256=%0h", packed_time_256, packed_time_256_ref);
256 …$display(" %s packed_time_256=%0h,packed_time_256=%0h", name, packed_time_256, packed_time_256_ref…
295 packed_time_256 = 0;
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H A Dt_stream_integer_type.out25 123 | packed_time_256 = {<<64{time_in}};
59 …r ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 25…
61 133 | {<<64{time_out}} = packed_time_256;
117 155 | packed_time_256 = {<<time{time_in}};
121 155 | packed_time_256 = {<<time{time_in}};