| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1420 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1438 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1441 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1442 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1448 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1453 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1473 pbs_min), 2); in ddr3_set_pbs_results()
1485 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1488 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1420 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1438 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1441 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1442 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1448 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1453 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1473 pbs_min), 2); in ddr3_set_pbs_results()
1485 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1488 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1420 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1438 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1441 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1442 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1448 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1453 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1473 pbs_min), 2); in ddr3_set_pbs_results()
1485 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1488 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1420 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1438 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1441 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1442 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1448 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1453 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1473 pbs_min), 2); in ddr3_set_pbs_results()
1485 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1488 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 1421 u32 pbs_min; /* minimal pbs val per pup */ in ddr3_set_pbs_results() local
1439 pbs_min = MAX_PBS; in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1449 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1454 DEBUG_PBS_FULL_D(pbs_min, 2); in ddr3_set_pbs_results()
1474 pbs_min), 2); in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
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