| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()
537 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) in decode_intpll()
540 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { in decode_intpll()
607 if ((pll_gnrl_ctl & pll_clke_mask) == 0) in decode_intpll()
654 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) in decode_fracpll()
657 if ((pll_gnrl_ctl & RST_MASK) == 0) in decode_fracpll()
663 if (pll_gnrl_ctl & BYPASS_MASK) in decode_fracpll()
666 if (!(pll_gnrl_ctl & LOCK_STATUS)) { in decode_fracpll()
[all …]
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