| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 77 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
81 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
82 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
83 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
84 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
85 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
87 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
89 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
92 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
94 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 77 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
81 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
82 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
83 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
84 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
85 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
87 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
89 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
92 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
94 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 77 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
81 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
82 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
83 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
84 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
85 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
87 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
89 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
92 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
94 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 77 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
81 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
82 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
83 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
84 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
85 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
87 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
89 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
92 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
94 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
87 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
88 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
89 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
90 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
91 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
93 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
95 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
100 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
[all …]
|