1 /** 2 * @file 3 * @brief Function prototypes for the new opcode functions. 4 * @note DO NOT EDIT THIS FILE, your changes will be lost. 5 * Edit ir/be/ia32/ia32_spec.pl instead. 6 * created by: ir/be/scripts/generate_new_opcodes.pl ir/be/ia32/ia32_spec.pl ir/be/ia32 7 * @date Mon Nov 19 18:12:23 2012 8 */ 9 #ifndef FIRM_BE_IA32_GEN_IA32_NEW_NODES_H 10 #define FIRM_BE_IA32_GEN_IA32_NEW_NODES_H 11 12 typedef enum ia32_opcodes { 13 iro_ia32_xZero, 14 iro_ia32_FldCW, 15 iro_ia32_fadd, 16 iro_ia32_ShrMem, 17 iro_ia32_Immediate, 18 iro_ia32_CvtSI2SS, 19 iro_ia32_Bsf, 20 iro_ia32_LdTls, 21 iro_ia32_ShlD, 22 iro_ia32_PopEbp, 23 iro_ia32_Inc, 24 iro_ia32_xStore, 25 iro_ia32_xxLoad, 26 iro_ia32_xAnd, 27 iro_ia32_GetEIP, 28 iro_ia32_xAdd, 29 iro_ia32_xPsllq, 30 iro_ia32_xxStore, 31 iro_ia32_Call, 32 iro_ia32_FnstCWNOP, 33 iro_ia32_XorMem8Bit, 34 iro_ia32_fldl2t, 35 iro_ia32_fisttp, 36 iro_ia32_DecMem, 37 iro_ia32_emms, 38 iro_ia32_xLoad, 39 iro_ia32_l_FloattoLL, 40 iro_ia32_CvtSI2SD, 41 iro_ia32_XorMem, 42 iro_ia32_CopyB, 43 iro_ia32_Xor0, 44 iro_ia32_Sar, 45 iro_ia32_Div, 46 iro_ia32_fpushCopy, 47 iro_ia32_Stc, 48 iro_ia32_Fucomi, 49 iro_ia32_fldl2e, 50 iro_ia32_Enter, 51 iro_ia32_fmul, 52 iro_ia32_l_IMul, 53 iro_ia32_NoReg_XMM, 54 iro_ia32_xMax, 55 iro_ia32_OrMem8Bit, 56 iro_ia32_Prefetch1, 57 iro_ia32_fsub, 58 iro_ia32_Lea, 59 iro_ia32_FtstFnstsw, 60 iro_ia32_NotMem, 61 iro_ia32_Sbb0, 62 iro_ia32_Bt, 63 iro_ia32_Or, 64 iro_ia32_Xor, 65 iro_ia32_CopyB_i, 66 iro_ia32_IncMem, 67 iro_ia32_xAllOnes, 68 iro_ia32_Breakpoint, 69 iro_ia32_ClimbFrame, 70 iro_ia32_ffreep, 71 iro_ia32_SubMem, 72 iro_ia32_AddMem, 73 iro_ia32_ShlMem, 74 iro_ia32_fdiv, 75 iro_ia32_Outport, 76 iro_ia32_xMin, 77 iro_ia32_fist, 78 iro_ia32_xXor, 79 iro_ia32_IJmp, 80 iro_ia32_NegMem, 81 iro_ia32_CMovcc, 82 iro_ia32_Mul, 83 iro_ia32_Sahf, 84 iro_ia32_SubMem8Bit, 85 iro_ia32_AddMem8Bit, 86 iro_ia32_fst, 87 iro_ia32_FucomppFnstsw, 88 iro_ia32_RorMem, 89 iro_ia32_fpush, 90 iro_ia32_fild, 91 iro_ia32_xOr, 92 iro_ia32_Conv_I2I8Bit, 93 iro_ia32_Store, 94 iro_ia32_fldln2, 95 iro_ia32_SwitchJmp, 96 iro_ia32_IMul, 97 iro_ia32_Ucomi, 98 iro_ia32_fldz, 99 iro_ia32_Store8Bit, 100 iro_ia32_fpop, 101 iro_ia32_l_Sub, 102 iro_ia32_Sbb, 103 iro_ia32_FucomFnstsw, 104 iro_ia32_xMul, 105 iro_ia32_Push, 106 iro_ia32_xPslld, 107 iro_ia32_Cmp, 108 iro_ia32_xSub, 109 iro_ia32_xMovd, 110 iro_ia32_Cltd, 111 iro_ia32_xPsrld, 112 iro_ia32_PushEax, 113 iro_ia32_XorHighLow, 114 iro_ia32_xPzero, 115 iro_ia32_Rol, 116 iro_ia32_Cmc, 117 iro_ia32_Cmp8Bit, 118 iro_ia32_xDiv, 119 iro_ia32_xUnknown, 120 iro_ia32_Test8Bit, 121 iro_ia32_Sub, 122 iro_ia32_PrefetchNTA, 123 iro_ia32_Shr, 124 iro_ia32_fprem, 125 iro_ia32_IDiv, 126 iro_ia32_l_Adc, 127 iro_ia32_Setcc, 128 iro_ia32_l_LLtoFloat, 129 iro_ia32_ProduceVal, 130 iro_ia32_Bswap, 131 iro_ia32_SetccMem, 132 iro_ia32_Test, 133 iro_ia32_l_Add, 134 iro_ia32_AddSP, 135 iro_ia32_RolMem, 136 iro_ia32_Conv_I2FP, 137 iro_ia32_Conv_FP2FP, 138 iro_ia32_ChangeCW, 139 iro_ia32_Prefetch2, 140 iro_ia32_NoReg_GP, 141 iro_ia32_Const, 142 iro_ia32_Minus64Bit, 143 iro_ia32_Jmp, 144 iro_ia32_FnstCW, 145 iro_ia32_Prefetch0, 146 iro_ia32_OrMem, 147 iro_ia32_fldlg2, 148 iro_ia32_fld1, 149 iro_ia32_Conv_FP2I, 150 iro_ia32_Popcnt, 151 iro_ia32_Ror, 152 iro_ia32_Shl, 153 iro_ia32_AndMem8Bit, 154 iro_ia32_Add, 155 iro_ia32_SubSP, 156 iro_ia32_PrefetchW, 157 iro_ia32_Conv_I2I, 158 iro_ia32_fxch, 159 iro_ia32_fchs, 160 iro_ia32_ShrD, 161 iro_ia32_Unknown, 162 iro_ia32_UD2, 163 iro_ia32_Cwtl, 164 iro_ia32_fabs, 165 iro_ia32_fldpi, 166 iro_ia32_Leave, 167 iro_ia32_Neg, 168 iro_ia32_IMul1OP, 169 iro_ia32_PopMem, 170 iro_ia32_fld, 171 iro_ia32_Dec, 172 iro_ia32_Pop, 173 iro_ia32_CopyEbpEsp, 174 iro_ia32_Not, 175 iro_ia32_NoReg_FP, 176 iro_ia32_AndMem, 177 iro_ia32_femms, 178 iro_ia32_xStoreSimple, 179 iro_ia32_And, 180 iro_ia32_Jcc, 181 iro_ia32_Asm, 182 iro_ia32_l_Sbb, 183 iro_ia32_Bsr, 184 iro_ia32_Bswap16, 185 iro_ia32_Inport, 186 iro_ia32_SarMem, 187 iro_ia32_RepPrefix, 188 iro_ia32_Adc, 189 iro_ia32_l_Mul, 190 iro_ia32_xAndNot, 191 iro_ia32_Load, 192 iro_ia32_Prefetch, 193 iro_ia32_last_generated, 194 iro_ia32_last = iro_ia32_last_generated 195 } ia32_opcodes; 196 197 int is_ia32_irn(const ir_node *node); 198 int is_ia32_op(const ir_op *op); 199 200 int get_ia32_opcode_first(void); 201 int get_ia32_opcode_last(void); 202 int get_ia32_irn_opcode(const ir_node *node); 203 void ia32_create_opcodes(const arch_irn_ops_t *be_ops); 204 void ia32_free_opcodes(void); 205 extern ir_op *op_ia32_xZero; 206 ir_op *get_op_ia32_xZero(void); 207 int is_ia32_xZero(const ir_node *n); 208 /** 209 * construct xZero node 210 */ 211 ir_node *new_bd_ia32_xZero(dbg_info *dbgi, ir_node *block); 212 213 extern ir_op *op_ia32_FldCW; 214 ir_op *get_op_ia32_FldCW(void); 215 int is_ia32_FldCW(const ir_node *n); 216 /** 217 * construct FldCW node 218 */ 219 ir_node *new_bd_ia32_FldCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 220 221 extern ir_op *op_ia32_fadd; 222 ir_op *get_op_ia32_fadd(void); 223 int is_ia32_fadd(const ir_node *n); 224 /** 225 * construct fadd node 226 */ 227 ir_node *new_bd_ia32_fadd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw); 228 229 extern ir_op *op_ia32_ShrMem; 230 ir_op *get_op_ia32_ShrMem(void); 231 int is_ia32_ShrMem(const ir_node *n); 232 /** 233 * construct ShrMem node 234 */ 235 ir_node *new_bd_ia32_ShrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count); 236 237 extern ir_op *op_ia32_Immediate; 238 ir_op *get_op_ia32_Immediate(void); 239 int is_ia32_Immediate(const ir_node *n); 240 /** 241 * construct Immediate node 242 */ 243 ir_node *new_bd_ia32_Immediate(dbg_info *dbgi, ir_node *block, ir_entity *symconst, int symconst_sign, int no_pic_adjust, long offset); 244 245 extern ir_op *op_ia32_CvtSI2SS; 246 ir_op *get_op_ia32_CvtSI2SS(void); 247 int is_ia32_CvtSI2SS(const ir_node *n); 248 /** 249 * construct CvtSI2SS node 250 */ 251 ir_node *new_bd_ia32_CvtSI2SS(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 252 253 extern ir_op *op_ia32_Bsf; 254 ir_op *get_op_ia32_Bsf(void); 255 int is_ia32_Bsf(const ir_node *n); 256 /** 257 * construct Bsf node 258 */ 259 ir_node *new_bd_ia32_Bsf(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand); 260 261 extern ir_op *op_ia32_LdTls; 262 ir_op *get_op_ia32_LdTls(void); 263 int is_ia32_LdTls(const ir_node *n); 264 /** 265 * construct LdTls node 266 */ 267 ir_node *new_bd_ia32_LdTls(dbg_info *dbgi, ir_node *block); 268 269 extern ir_op *op_ia32_ShlD; 270 ir_op *get_op_ia32_ShlD(void); 271 int is_ia32_ShlD(const ir_node *n); 272 /** 273 * construct ShlD node 274 */ 275 ir_node *new_bd_ia32_ShlD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count); 276 277 extern ir_op *op_ia32_PopEbp; 278 ir_op *get_op_ia32_PopEbp(void); 279 int is_ia32_PopEbp(const ir_node *n); 280 /** 281 * construct PopEbp node 282 */ 283 ir_node *new_bd_ia32_PopEbp(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack); 284 285 extern ir_op *op_ia32_Inc; 286 ir_op *get_op_ia32_Inc(void); 287 int is_ia32_Inc(const ir_node *n); 288 /** 289 * construct Inc node 290 */ 291 ir_node *new_bd_ia32_Inc(dbg_info *dbgi, ir_node *block, ir_node *val); 292 293 extern ir_op *op_ia32_xStore; 294 ir_op *get_op_ia32_xStore(void); 295 int is_ia32_xStore(const ir_node *n); 296 /** 297 * construct xStore node 298 */ 299 ir_node *new_bd_ia32_xStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 300 301 extern ir_op *op_ia32_xxLoad; 302 ir_op *get_op_ia32_xxLoad(void); 303 int is_ia32_xxLoad(const ir_node *n); 304 /** 305 * construct xxLoad node 306 */ 307 ir_node *new_bd_ia32_xxLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 308 309 extern ir_op *op_ia32_xAnd; 310 ir_op *get_op_ia32_xAnd(void); 311 int is_ia32_xAnd(const ir_node *n); 312 /** 313 * construct xAnd node 314 */ 315 ir_node *new_bd_ia32_xAnd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 316 317 extern ir_op *op_ia32_GetEIP; 318 ir_op *get_op_ia32_GetEIP(void); 319 int is_ia32_GetEIP(const ir_node *n); 320 /** 321 * construct GetEIP node 322 */ 323 ir_node *new_bd_ia32_GetEIP(dbg_info *dbgi, ir_node *block); 324 325 extern ir_op *op_ia32_xAdd; 326 ir_op *get_op_ia32_xAdd(void); 327 int is_ia32_xAdd(const ir_node *n); 328 /** 329 * construct xAdd node 330 */ 331 ir_node *new_bd_ia32_xAdd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 332 333 extern ir_op *op_ia32_xPsllq; 334 ir_op *get_op_ia32_xPsllq(void); 335 int is_ia32_xPsllq(const ir_node *n); 336 /** 337 * construct xPsllq node 338 */ 339 ir_node *new_bd_ia32_xPsllq(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1); 340 341 extern ir_op *op_ia32_xxStore; 342 ir_op *get_op_ia32_xxStore(void); 343 int is_ia32_xxStore(const ir_node *n); 344 /** 345 * construct xxStore node 346 */ 347 ir_node *new_bd_ia32_xxStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 348 349 extern ir_op *op_ia32_Call; 350 ir_op *get_op_ia32_Call(void); 351 int is_ia32_Call(const ir_node *n); 352 /** 353 * construct Call node 354 */ 355 ir_node *new_bd_ia32_Call(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *addr, ir_node *stack, ir_node *fpcw, ir_node *eax, ir_node *ecx, ir_node *edx, unsigned pop, ir_type *call_tp); 356 357 extern ir_op *op_ia32_FnstCWNOP; 358 ir_op *get_op_ia32_FnstCWNOP(void); 359 int is_ia32_FnstCWNOP(const ir_node *n); 360 /** 361 * construct FnstCWNOP node 362 */ 363 ir_node *new_bd_ia32_FnstCWNOP(dbg_info *dbgi, ir_node *block, ir_node *fpcw); 364 365 extern ir_op *op_ia32_XorMem8Bit; 366 ir_op *get_op_ia32_XorMem8Bit(void); 367 int is_ia32_XorMem8Bit(const ir_node *n); 368 /** 369 * construct XorMem8Bit node 370 */ 371 ir_node *new_bd_ia32_XorMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 372 373 extern ir_op *op_ia32_fldl2t; 374 ir_op *get_op_ia32_fldl2t(void); 375 int is_ia32_fldl2t(const ir_node *n); 376 /** 377 * construct fldl2t node 378 */ 379 ir_node *new_bd_ia32_fldl2t(dbg_info *dbgi, ir_node *block); 380 381 extern ir_op *op_ia32_fisttp; 382 ir_op *get_op_ia32_fisttp(void); 383 int is_ia32_fisttp(const ir_node *n); 384 /** 385 * construct fisttp node 386 */ 387 ir_node *new_bd_ia32_fisttp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 388 389 extern ir_op *op_ia32_DecMem; 390 ir_op *get_op_ia32_DecMem(void); 391 int is_ia32_DecMem(const ir_node *n); 392 /** 393 * construct DecMem node 394 */ 395 ir_node *new_bd_ia32_DecMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 396 397 extern ir_op *op_ia32_emms; 398 ir_op *get_op_ia32_emms(void); 399 int is_ia32_emms(const ir_node *n); 400 /** 401 * construct emms node 402 */ 403 ir_node *new_bd_ia32_emms(dbg_info *dbgi, ir_node *block); 404 405 extern ir_op *op_ia32_xLoad; 406 ir_op *get_op_ia32_xLoad(void); 407 int is_ia32_xLoad(const ir_node *n); 408 /** 409 * construct xLoad node 410 */ 411 ir_node *new_bd_ia32_xLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_mode *load_mode); 412 413 extern ir_op *op_ia32_l_FloattoLL; 414 ir_op *get_op_ia32_l_FloattoLL(void); 415 int is_ia32_l_FloattoLL(const ir_node *n); 416 /** 417 * construct l_FloattoLL node 418 */ 419 ir_node *new_bd_ia32_l_FloattoLL(dbg_info *dbgi, ir_node *block, ir_node *val); 420 421 extern ir_op *op_ia32_CvtSI2SD; 422 ir_op *get_op_ia32_CvtSI2SD(void); 423 int is_ia32_CvtSI2SD(const ir_node *n); 424 /** 425 * construct CvtSI2SD node 426 */ 427 ir_node *new_bd_ia32_CvtSI2SD(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 428 429 extern ir_op *op_ia32_XorMem; 430 ir_op *get_op_ia32_XorMem(void); 431 int is_ia32_XorMem(const ir_node *n); 432 /** 433 * construct XorMem node 434 */ 435 ir_node *new_bd_ia32_XorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 436 437 extern ir_op *op_ia32_CopyB; 438 ir_op *get_op_ia32_CopyB(void); 439 int is_ia32_CopyB(const ir_node *n); 440 /** 441 * construct CopyB node 442 */ 443 ir_node *new_bd_ia32_CopyB(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *count, ir_node *mem, unsigned size); 444 445 extern ir_op *op_ia32_Xor0; 446 ir_op *get_op_ia32_Xor0(void); 447 int is_ia32_Xor0(const ir_node *n); 448 /** 449 * construct Xor0 node 450 */ 451 ir_node *new_bd_ia32_Xor0(dbg_info *dbgi, ir_node *block); 452 453 extern ir_op *op_ia32_Sar; 454 ir_op *get_op_ia32_Sar(void); 455 int is_ia32_Sar(const ir_node *n); 456 /** 457 * construct Sar node 458 */ 459 ir_node *new_bd_ia32_Sar(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count); 460 461 extern ir_op *op_ia32_Div; 462 ir_op *get_op_ia32_Div(void); 463 int is_ia32_Div(const ir_node *n); 464 /** 465 * construct Div node 466 */ 467 ir_node *new_bd_ia32_Div(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high); 468 469 extern ir_op *op_ia32_fpushCopy; 470 ir_op *get_op_ia32_fpushCopy(void); 471 int is_ia32_fpushCopy(const ir_node *n); 472 /** 473 * construct fpushCopy node 474 */ 475 ir_node *new_bd_ia32_fpushCopy(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_mode *mode); 476 477 extern ir_op *op_ia32_Stc; 478 ir_op *get_op_ia32_Stc(void); 479 int is_ia32_Stc(const ir_node *n); 480 /** 481 * construct Stc node 482 */ 483 ir_node *new_bd_ia32_Stc(dbg_info *dbgi, ir_node *block); 484 485 extern ir_op *op_ia32_Fucomi; 486 ir_op *get_op_ia32_Fucomi(void); 487 int is_ia32_Fucomi(const ir_node *n); 488 /** 489 * construct Fucomi node 490 */ 491 ir_node *new_bd_ia32_Fucomi(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted); 492 493 extern ir_op *op_ia32_fldl2e; 494 ir_op *get_op_ia32_fldl2e(void); 495 int is_ia32_fldl2e(const ir_node *n); 496 /** 497 * construct fldl2e node 498 */ 499 ir_node *new_bd_ia32_fldl2e(dbg_info *dbgi, ir_node *block); 500 501 extern ir_op *op_ia32_Enter; 502 ir_op *get_op_ia32_Enter(void); 503 int is_ia32_Enter(const ir_node *n); 504 /** 505 * construct Enter node 506 */ 507 ir_node *new_bd_ia32_Enter(dbg_info *dbgi, ir_node *block, ir_node *op0); 508 509 extern ir_op *op_ia32_fmul; 510 ir_op *get_op_ia32_fmul(void); 511 int is_ia32_fmul(const ir_node *n); 512 /** 513 * construct fmul node 514 */ 515 ir_node *new_bd_ia32_fmul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw); 516 517 extern ir_op *op_ia32_l_IMul; 518 ir_op *get_op_ia32_l_IMul(void); 519 int is_ia32_l_IMul(const ir_node *n); 520 /** 521 * construct l_IMul node 522 */ 523 ir_node *new_bd_ia32_l_IMul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right); 524 525 extern ir_op *op_ia32_NoReg_XMM; 526 ir_op *get_op_ia32_NoReg_XMM(void); 527 int is_ia32_NoReg_XMM(const ir_node *n); 528 /** 529 * construct NoReg_XMM node 530 */ 531 ir_node *new_bd_ia32_NoReg_XMM(dbg_info *dbgi, ir_node *block); 532 533 extern ir_op *op_ia32_xMax; 534 ir_op *get_op_ia32_xMax(void); 535 int is_ia32_xMax(const ir_node *n); 536 /** 537 * construct xMax node 538 */ 539 ir_node *new_bd_ia32_xMax(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 540 541 extern ir_op *op_ia32_OrMem8Bit; 542 ir_op *get_op_ia32_OrMem8Bit(void); 543 int is_ia32_OrMem8Bit(const ir_node *n); 544 /** 545 * construct OrMem8Bit node 546 */ 547 ir_node *new_bd_ia32_OrMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 548 549 extern ir_op *op_ia32_Prefetch1; 550 ir_op *get_op_ia32_Prefetch1(void); 551 int is_ia32_Prefetch1(const ir_node *n); 552 /** 553 * construct Prefetch1 node 554 */ 555 ir_node *new_bd_ia32_Prefetch1(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 556 557 extern ir_op *op_ia32_fsub; 558 ir_op *get_op_ia32_fsub(void); 559 int is_ia32_fsub(const ir_node *n); 560 /** 561 * construct fsub node 562 */ 563 ir_node *new_bd_ia32_fsub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *fpcw); 564 565 extern ir_op *op_ia32_Lea; 566 ir_op *get_op_ia32_Lea(void); 567 int is_ia32_Lea(const ir_node *n); 568 /** 569 * construct Lea node 570 */ 571 ir_node *new_bd_ia32_Lea(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index); 572 573 extern ir_op *op_ia32_FtstFnstsw; 574 ir_op *get_op_ia32_FtstFnstsw(void); 575 int is_ia32_FtstFnstsw(const ir_node *n); 576 /** 577 * construct FtstFnstsw node 578 */ 579 ir_node *new_bd_ia32_FtstFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, bool ins_permuted); 580 581 extern ir_op *op_ia32_NotMem; 582 ir_op *get_op_ia32_NotMem(void); 583 int is_ia32_NotMem(const ir_node *n); 584 /** 585 * construct NotMem node 586 */ 587 ir_node *new_bd_ia32_NotMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 588 589 extern ir_op *op_ia32_Sbb0; 590 ir_op *get_op_ia32_Sbb0(void); 591 int is_ia32_Sbb0(const ir_node *n); 592 /** 593 * construct Sbb0 node 594 */ 595 ir_node *new_bd_ia32_Sbb0(dbg_info *dbgi, ir_node *block, ir_node *op0); 596 597 extern ir_op *op_ia32_Bt; 598 ir_op *get_op_ia32_Bt(void); 599 int is_ia32_Bt(const ir_node *n); 600 /** 601 * construct Bt node 602 */ 603 ir_node *new_bd_ia32_Bt(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right); 604 605 extern ir_op *op_ia32_Or; 606 ir_op *get_op_ia32_Or(void); 607 int is_ia32_Or(const ir_node *n); 608 /** 609 * construct Or node 610 */ 611 ir_node *new_bd_ia32_Or(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 612 613 extern ir_op *op_ia32_Xor; 614 ir_op *get_op_ia32_Xor(void); 615 int is_ia32_Xor(const ir_node *n); 616 /** 617 * construct Xor node 618 */ 619 ir_node *new_bd_ia32_Xor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 620 621 extern ir_op *op_ia32_CopyB_i; 622 ir_op *get_op_ia32_CopyB_i(void); 623 int is_ia32_CopyB_i(const ir_node *n); 624 /** 625 * construct CopyB_i node 626 */ 627 ir_node *new_bd_ia32_CopyB_i(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *mem, unsigned size); 628 629 extern ir_op *op_ia32_IncMem; 630 ir_op *get_op_ia32_IncMem(void); 631 int is_ia32_IncMem(const ir_node *n); 632 /** 633 * construct IncMem node 634 */ 635 ir_node *new_bd_ia32_IncMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 636 637 extern ir_op *op_ia32_xAllOnes; 638 ir_op *get_op_ia32_xAllOnes(void); 639 int is_ia32_xAllOnes(const ir_node *n); 640 /** 641 * construct xAllOnes node 642 */ 643 ir_node *new_bd_ia32_xAllOnes(dbg_info *dbgi, ir_node *block); 644 645 extern ir_op *op_ia32_Breakpoint; 646 ir_op *get_op_ia32_Breakpoint(void); 647 int is_ia32_Breakpoint(const ir_node *n); 648 /** 649 * construct Breakpoint node 650 */ 651 ir_node *new_bd_ia32_Breakpoint(dbg_info *dbgi, ir_node *block, ir_node *mem); 652 653 extern ir_op *op_ia32_ClimbFrame; 654 ir_op *get_op_ia32_ClimbFrame(void); 655 int is_ia32_ClimbFrame(const ir_node *n); 656 /** 657 * construct ClimbFrame node 658 */ 659 ir_node *new_bd_ia32_ClimbFrame(dbg_info *dbgi, ir_node *block, ir_node *frame, ir_node *cnt, ir_node *tmp, unsigned count); 660 661 extern ir_op *op_ia32_ffreep; 662 ir_op *get_op_ia32_ffreep(void); 663 int is_ia32_ffreep(const ir_node *n); 664 /** 665 * construct ffreep node 666 */ 667 ir_node *new_bd_ia32_ffreep(dbg_info *dbgi, ir_node *block); 668 669 extern ir_op *op_ia32_SubMem; 670 ir_op *get_op_ia32_SubMem(void); 671 int is_ia32_SubMem(const ir_node *n); 672 /** 673 * construct SubMem node 674 */ 675 ir_node *new_bd_ia32_SubMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *subtrahend); 676 677 extern ir_op *op_ia32_AddMem; 678 ir_op *get_op_ia32_AddMem(void); 679 int is_ia32_AddMem(const ir_node *n); 680 /** 681 * construct AddMem node 682 */ 683 ir_node *new_bd_ia32_AddMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 684 685 extern ir_op *op_ia32_ShlMem; 686 ir_op *get_op_ia32_ShlMem(void); 687 int is_ia32_ShlMem(const ir_node *n); 688 /** 689 * construct ShlMem node 690 */ 691 ir_node *new_bd_ia32_ShlMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count); 692 693 extern ir_op *op_ia32_fdiv; 694 ir_op *get_op_ia32_fdiv(void); 695 int is_ia32_fdiv(const ir_node *n); 696 /** 697 * construct fdiv node 698 */ 699 ir_node *new_bd_ia32_fdiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *dividend, ir_node *divisor, ir_node *fpcw); 700 701 extern ir_op *op_ia32_Outport; 702 ir_op *get_op_ia32_Outport(void); 703 int is_ia32_Outport(const ir_node *n); 704 /** 705 * construct Outport node 706 */ 707 ir_node *new_bd_ia32_Outport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *value, ir_node *mem); 708 709 extern ir_op *op_ia32_xMin; 710 ir_op *get_op_ia32_xMin(void); 711 int is_ia32_xMin(const ir_node *n); 712 /** 713 * construct xMin node 714 */ 715 ir_node *new_bd_ia32_xMin(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 716 717 extern ir_op *op_ia32_fist; 718 ir_op *get_op_ia32_fist(void); 719 int is_ia32_fist(const ir_node *n); 720 /** 721 * construct fist node 722 */ 723 ir_node *new_bd_ia32_fist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw); 724 725 extern ir_op *op_ia32_xXor; 726 ir_op *get_op_ia32_xXor(void); 727 int is_ia32_xXor(const ir_node *n); 728 /** 729 * construct xXor node 730 */ 731 ir_node *new_bd_ia32_xXor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 732 733 extern ir_op *op_ia32_IJmp; 734 ir_op *get_op_ia32_IJmp(void); 735 int is_ia32_IJmp(const ir_node *n); 736 /** 737 * construct IJmp node 738 */ 739 ir_node *new_bd_ia32_IJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *target); 740 741 extern ir_op *op_ia32_NegMem; 742 ir_op *get_op_ia32_NegMem(void); 743 int is_ia32_NegMem(const ir_node *n); 744 /** 745 * construct NegMem node 746 */ 747 ir_node *new_bd_ia32_NegMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 748 749 extern ir_op *op_ia32_CMovcc; 750 ir_op *get_op_ia32_CMovcc(void); 751 int is_ia32_CMovcc(const ir_node *n); 752 /** 753 * construct CMovcc node 754 */ 755 ir_node *new_bd_ia32_CMovcc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val_false, ir_node *val_true, ir_node *eflags, ia32_condition_code_t condition_code); 756 757 extern ir_op *op_ia32_Mul; 758 ir_op *get_op_ia32_Mul(void); 759 int is_ia32_Mul(const ir_node *n); 760 /** 761 * construct Mul node 762 */ 763 ir_node *new_bd_ia32_Mul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 764 765 extern ir_op *op_ia32_Sahf; 766 ir_op *get_op_ia32_Sahf(void); 767 int is_ia32_Sahf(const ir_node *n); 768 /** 769 * construct Sahf node 770 */ 771 ir_node *new_bd_ia32_Sahf(dbg_info *dbgi, ir_node *block, ir_node *val); 772 773 extern ir_op *op_ia32_SubMem8Bit; 774 ir_op *get_op_ia32_SubMem8Bit(void); 775 int is_ia32_SubMem8Bit(const ir_node *n); 776 /** 777 * construct SubMem8Bit node 778 */ 779 ir_node *new_bd_ia32_SubMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *subtrahend); 780 781 extern ir_op *op_ia32_AddMem8Bit; 782 ir_op *get_op_ia32_AddMem8Bit(void); 783 int is_ia32_AddMem8Bit(const ir_node *n); 784 /** 785 * construct AddMem8Bit node 786 */ 787 ir_node *new_bd_ia32_AddMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 788 789 extern ir_op *op_ia32_fst; 790 ir_op *get_op_ia32_fst(void); 791 int is_ia32_fst(const ir_node *n); 792 /** 793 * construct fst node 794 */ 795 ir_node *new_bd_ia32_fst(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *store_mode); 796 797 extern ir_op *op_ia32_FucomppFnstsw; 798 ir_op *get_op_ia32_FucomppFnstsw(void); 799 int is_ia32_FucomppFnstsw(const ir_node *n); 800 /** 801 * construct FucomppFnstsw node 802 */ 803 ir_node *new_bd_ia32_FucomppFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted); 804 805 extern ir_op *op_ia32_RorMem; 806 ir_op *get_op_ia32_RorMem(void); 807 int is_ia32_RorMem(const ir_node *n); 808 /** 809 * construct RorMem node 810 */ 811 ir_node *new_bd_ia32_RorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count); 812 813 extern ir_op *op_ia32_fpush; 814 ir_op *get_op_ia32_fpush(void); 815 int is_ia32_fpush(const ir_node *n); 816 /** 817 * construct fpush node 818 */ 819 ir_node *new_bd_ia32_fpush(dbg_info *dbgi, ir_node *block); 820 821 extern ir_op *op_ia32_fild; 822 ir_op *get_op_ia32_fild(void); 823 int is_ia32_fild(const ir_node *n); 824 /** 825 * construct fild node 826 */ 827 ir_node *new_bd_ia32_fild(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 828 829 extern ir_op *op_ia32_xOr; 830 ir_op *get_op_ia32_xOr(void); 831 int is_ia32_xOr(const ir_node *n); 832 /** 833 * construct xOr node 834 */ 835 ir_node *new_bd_ia32_xOr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 836 837 extern ir_op *op_ia32_Conv_I2I8Bit; 838 ir_op *get_op_ia32_Conv_I2I8Bit(void); 839 int is_ia32_Conv_I2I8Bit(const ir_node *n); 840 /** 841 * construct Conv_I2I8Bit node 842 */ 843 ir_node *new_bd_ia32_Conv_I2I8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *smaller_mode); 844 845 extern ir_op *op_ia32_Store; 846 ir_op *get_op_ia32_Store(void); 847 int is_ia32_Store(const ir_node *n); 848 /** 849 * construct Store node 850 */ 851 ir_node *new_bd_ia32_Store(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 852 853 extern ir_op *op_ia32_fldln2; 854 ir_op *get_op_ia32_fldln2(void); 855 int is_ia32_fldln2(const ir_node *n); 856 /** 857 * construct fldln2 node 858 */ 859 ir_node *new_bd_ia32_fldln2(dbg_info *dbgi, ir_node *block); 860 861 extern ir_op *op_ia32_SwitchJmp; 862 ir_op *get_op_ia32_SwitchJmp(void); 863 int is_ia32_SwitchJmp(const ir_node *n); 864 /** 865 * construct SwitchJmp node 866 */ 867 ir_node *new_bd_ia32_SwitchJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, int n_res, const ir_switch_table *switch_table); 868 869 extern ir_op *op_ia32_IMul; 870 ir_op *get_op_ia32_IMul(void); 871 int is_ia32_IMul(const ir_node *n); 872 /** 873 * construct IMul node 874 */ 875 ir_node *new_bd_ia32_IMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 876 877 extern ir_op *op_ia32_Ucomi; 878 ir_op *get_op_ia32_Ucomi(void); 879 int is_ia32_Ucomi(const ir_node *n); 880 /** 881 * construct Ucomi node 882 */ 883 ir_node *new_bd_ia32_Ucomi(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted); 884 885 extern ir_op *op_ia32_fldz; 886 ir_op *get_op_ia32_fldz(void); 887 int is_ia32_fldz(const ir_node *n); 888 /** 889 * construct fldz node 890 */ 891 ir_node *new_bd_ia32_fldz(dbg_info *dbgi, ir_node *block); 892 893 extern ir_op *op_ia32_Store8Bit; 894 ir_op *get_op_ia32_Store8Bit(void); 895 int is_ia32_Store8Bit(const ir_node *n); 896 /** 897 * construct Store8Bit node 898 */ 899 ir_node *new_bd_ia32_Store8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 900 901 extern ir_op *op_ia32_fpop; 902 ir_op *get_op_ia32_fpop(void); 903 int is_ia32_fpop(const ir_node *n); 904 /** 905 * construct fpop node 906 */ 907 ir_node *new_bd_ia32_fpop(dbg_info *dbgi, ir_node *block); 908 909 extern ir_op *op_ia32_l_Sub; 910 ir_op *get_op_ia32_l_Sub(void); 911 int is_ia32_l_Sub(const ir_node *n); 912 /** 913 * construct l_Sub node 914 */ 915 ir_node *new_bd_ia32_l_Sub(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_mode *mode); 916 917 extern ir_op *op_ia32_Sbb; 918 ir_op *get_op_ia32_Sbb(void); 919 int is_ia32_Sbb(const ir_node *n); 920 /** 921 * construct Sbb node 922 */ 923 ir_node *new_bd_ia32_Sbb(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *eflags); 924 925 extern ir_op *op_ia32_FucomFnstsw; 926 ir_op *get_op_ia32_FucomFnstsw(void); 927 int is_ia32_FucomFnstsw(const ir_node *n); 928 /** 929 * construct FucomFnstsw node 930 */ 931 ir_node *new_bd_ia32_FucomFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted); 932 933 extern ir_op *op_ia32_xMul; 934 ir_op *get_op_ia32_xMul(void); 935 int is_ia32_xMul(const ir_node *n); 936 /** 937 * construct xMul node 938 */ 939 ir_node *new_bd_ia32_xMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 940 941 extern ir_op *op_ia32_Push; 942 ir_op *get_op_ia32_Push(void); 943 int is_ia32_Push(const ir_node *n); 944 /** 945 * construct Push node 946 */ 947 ir_node *new_bd_ia32_Push(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *stack); 948 949 extern ir_op *op_ia32_xPslld; 950 ir_op *get_op_ia32_xPslld(void); 951 int is_ia32_xPslld(const ir_node *n); 952 /** 953 * construct xPslld node 954 */ 955 ir_node *new_bd_ia32_xPslld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1); 956 957 extern ir_op *op_ia32_Cmp; 958 ir_op *get_op_ia32_Cmp(void); 959 int is_ia32_Cmp(const ir_node *n); 960 /** 961 * construct Cmp node 962 */ 963 ir_node *new_bd_ia32_Cmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted); 964 965 extern ir_op *op_ia32_xSub; 966 ir_op *get_op_ia32_xSub(void); 967 int is_ia32_xSub(const ir_node *n); 968 /** 969 * construct xSub node 970 */ 971 ir_node *new_bd_ia32_xSub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend); 972 973 extern ir_op *op_ia32_xMovd; 974 ir_op *get_op_ia32_xMovd(void); 975 int is_ia32_xMovd(const ir_node *n); 976 /** 977 * construct xMovd node 978 */ 979 ir_node *new_bd_ia32_xMovd(dbg_info *dbgi, ir_node *block, ir_node *op0); 980 981 extern ir_op *op_ia32_Cltd; 982 ir_op *get_op_ia32_Cltd(void); 983 int is_ia32_Cltd(const ir_node *n); 984 /** 985 * construct Cltd node 986 */ 987 ir_node *new_bd_ia32_Cltd(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *clobbered); 988 989 extern ir_op *op_ia32_xPsrld; 990 ir_op *get_op_ia32_xPsrld(void); 991 int is_ia32_xPsrld(const ir_node *n); 992 /** 993 * construct xPsrld node 994 */ 995 ir_node *new_bd_ia32_xPsrld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1); 996 997 extern ir_op *op_ia32_PushEax; 998 ir_op *get_op_ia32_PushEax(void); 999 int is_ia32_PushEax(const ir_node *n); 1000 /** 1001 * construct PushEax node 1002 */ 1003 ir_node *new_bd_ia32_PushEax(dbg_info *dbgi, ir_node *block, ir_node *stack); 1004 1005 extern ir_op *op_ia32_XorHighLow; 1006 ir_op *get_op_ia32_XorHighLow(void); 1007 int is_ia32_XorHighLow(const ir_node *n); 1008 /** 1009 * construct XorHighLow node 1010 */ 1011 ir_node *new_bd_ia32_XorHighLow(dbg_info *dbgi, ir_node *block, ir_node *value); 1012 1013 extern ir_op *op_ia32_xPzero; 1014 ir_op *get_op_ia32_xPzero(void); 1015 int is_ia32_xPzero(const ir_node *n); 1016 /** 1017 * construct xPzero node 1018 */ 1019 ir_node *new_bd_ia32_xPzero(dbg_info *dbgi, ir_node *block); 1020 1021 extern ir_op *op_ia32_Rol; 1022 ir_op *get_op_ia32_Rol(void); 1023 int is_ia32_Rol(const ir_node *n); 1024 /** 1025 * construct Rol node 1026 */ 1027 ir_node *new_bd_ia32_Rol(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count); 1028 1029 extern ir_op *op_ia32_Cmc; 1030 ir_op *get_op_ia32_Cmc(void); 1031 int is_ia32_Cmc(const ir_node *n); 1032 /** 1033 * construct Cmc node 1034 */ 1035 ir_node *new_bd_ia32_Cmc(dbg_info *dbgi, ir_node *block, ir_node *op0); 1036 1037 extern ir_op *op_ia32_Cmp8Bit; 1038 ir_op *get_op_ia32_Cmp8Bit(void); 1039 int is_ia32_Cmp8Bit(const ir_node *n); 1040 /** 1041 * construct Cmp8Bit node 1042 */ 1043 ir_node *new_bd_ia32_Cmp8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted); 1044 1045 extern ir_op *op_ia32_xDiv; 1046 ir_op *get_op_ia32_xDiv(void); 1047 int is_ia32_xDiv(const ir_node *n); 1048 /** 1049 * construct xDiv node 1050 */ 1051 ir_node *new_bd_ia32_xDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *dividend, ir_node *divisor); 1052 1053 extern ir_op *op_ia32_xUnknown; 1054 ir_op *get_op_ia32_xUnknown(void); 1055 int is_ia32_xUnknown(const ir_node *n); 1056 /** 1057 * construct xUnknown node 1058 */ 1059 ir_node *new_bd_ia32_xUnknown(dbg_info *dbgi, ir_node *block); 1060 1061 extern ir_op *op_ia32_Test8Bit; 1062 ir_op *get_op_ia32_Test8Bit(void); 1063 int is_ia32_Test8Bit(const ir_node *n); 1064 /** 1065 * construct Test8Bit node 1066 */ 1067 ir_node *new_bd_ia32_Test8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted); 1068 1069 extern ir_op *op_ia32_Sub; 1070 ir_op *get_op_ia32_Sub(void); 1071 int is_ia32_Sub(const ir_node *n); 1072 /** 1073 * construct Sub node 1074 */ 1075 ir_node *new_bd_ia32_Sub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend); 1076 1077 extern ir_op *op_ia32_PrefetchNTA; 1078 ir_op *get_op_ia32_PrefetchNTA(void); 1079 int is_ia32_PrefetchNTA(const ir_node *n); 1080 /** 1081 * construct PrefetchNTA node 1082 */ 1083 ir_node *new_bd_ia32_PrefetchNTA(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 1084 1085 extern ir_op *op_ia32_Shr; 1086 ir_op *get_op_ia32_Shr(void); 1087 int is_ia32_Shr(const ir_node *n); 1088 /** 1089 * construct Shr node 1090 */ 1091 ir_node *new_bd_ia32_Shr(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count); 1092 1093 extern ir_op *op_ia32_fprem; 1094 ir_op *get_op_ia32_fprem(void); 1095 int is_ia32_fprem(const ir_node *n); 1096 /** 1097 * construct fprem node 1098 */ 1099 ir_node *new_bd_ia32_fprem(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *fpcw); 1100 1101 extern ir_op *op_ia32_IDiv; 1102 ir_op *get_op_ia32_IDiv(void); 1103 int is_ia32_IDiv(const ir_node *n); 1104 /** 1105 * construct IDiv node 1106 */ 1107 ir_node *new_bd_ia32_IDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high); 1108 1109 extern ir_op *op_ia32_l_Adc; 1110 ir_op *get_op_ia32_l_Adc(void); 1111 int is_ia32_l_Adc(const ir_node *n); 1112 /** 1113 * construct l_Adc node 1114 */ 1115 ir_node *new_bd_ia32_l_Adc(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *eflags, ir_mode *mode); 1116 1117 extern ir_op *op_ia32_Setcc; 1118 ir_op *get_op_ia32_Setcc(void); 1119 int is_ia32_Setcc(const ir_node *n); 1120 /** 1121 * construct Setcc node 1122 */ 1123 ir_node *new_bd_ia32_Setcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, ia32_condition_code_t condition_code); 1124 1125 extern ir_op *op_ia32_l_LLtoFloat; 1126 ir_op *get_op_ia32_l_LLtoFloat(void); 1127 int is_ia32_l_LLtoFloat(const ir_node *n); 1128 /** 1129 * construct l_LLtoFloat node 1130 */ 1131 ir_node *new_bd_ia32_l_LLtoFloat(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_mode *mode); 1132 1133 extern ir_op *op_ia32_ProduceVal; 1134 ir_op *get_op_ia32_ProduceVal(void); 1135 int is_ia32_ProduceVal(const ir_node *n); 1136 /** 1137 * construct ProduceVal node 1138 */ 1139 ir_node *new_bd_ia32_ProduceVal(dbg_info *dbgi, ir_node *block); 1140 1141 extern ir_op *op_ia32_Bswap; 1142 ir_op *get_op_ia32_Bswap(void); 1143 int is_ia32_Bswap(const ir_node *n); 1144 /** 1145 * construct Bswap node 1146 */ 1147 ir_node *new_bd_ia32_Bswap(dbg_info *dbgi, ir_node *block, ir_node *val); 1148 1149 extern ir_op *op_ia32_SetccMem; 1150 ir_op *get_op_ia32_SetccMem(void); 1151 int is_ia32_SetccMem(const ir_node *n); 1152 /** 1153 * construct SetccMem node 1154 */ 1155 ir_node *new_bd_ia32_SetccMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *eflags, ia32_condition_code_t condition_code); 1156 1157 extern ir_op *op_ia32_Test; 1158 ir_op *get_op_ia32_Test(void); 1159 int is_ia32_Test(const ir_node *n); 1160 /** 1161 * construct Test node 1162 */ 1163 ir_node *new_bd_ia32_Test(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted); 1164 1165 extern ir_op *op_ia32_l_Add; 1166 ir_op *get_op_ia32_l_Add(void); 1167 int is_ia32_l_Add(const ir_node *n); 1168 /** 1169 * construct l_Add node 1170 */ 1171 ir_node *new_bd_ia32_l_Add(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_mode *mode); 1172 1173 extern ir_op *op_ia32_AddSP; 1174 ir_op *get_op_ia32_AddSP(void); 1175 int is_ia32_AddSP(const ir_node *n); 1176 /** 1177 * construct AddSP node 1178 */ 1179 ir_node *new_bd_ia32_AddSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *size); 1180 1181 extern ir_op *op_ia32_RolMem; 1182 ir_op *get_op_ia32_RolMem(void); 1183 int is_ia32_RolMem(const ir_node *n); 1184 /** 1185 * construct RolMem node 1186 */ 1187 ir_node *new_bd_ia32_RolMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count); 1188 1189 extern ir_op *op_ia32_Conv_I2FP; 1190 ir_op *get_op_ia32_Conv_I2FP(void); 1191 int is_ia32_Conv_I2FP(const ir_node *n); 1192 /** 1193 * construct Conv_I2FP node 1194 */ 1195 ir_node *new_bd_ia32_Conv_I2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1196 1197 extern ir_op *op_ia32_Conv_FP2FP; 1198 ir_op *get_op_ia32_Conv_FP2FP(void); 1199 int is_ia32_Conv_FP2FP(const ir_node *n); 1200 /** 1201 * construct Conv_FP2FP node 1202 */ 1203 ir_node *new_bd_ia32_Conv_FP2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1204 1205 extern ir_op *op_ia32_ChangeCW; 1206 ir_op *get_op_ia32_ChangeCW(void); 1207 int is_ia32_ChangeCW(const ir_node *n); 1208 /** 1209 * construct ChangeCW node 1210 */ 1211 ir_node *new_bd_ia32_ChangeCW(dbg_info *dbgi, ir_node *block); 1212 1213 extern ir_op *op_ia32_Prefetch2; 1214 ir_op *get_op_ia32_Prefetch2(void); 1215 int is_ia32_Prefetch2(const ir_node *n); 1216 /** 1217 * construct Prefetch2 node 1218 */ 1219 ir_node *new_bd_ia32_Prefetch2(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 1220 1221 extern ir_op *op_ia32_NoReg_GP; 1222 ir_op *get_op_ia32_NoReg_GP(void); 1223 int is_ia32_NoReg_GP(const ir_node *n); 1224 /** 1225 * construct NoReg_GP node 1226 */ 1227 ir_node *new_bd_ia32_NoReg_GP(dbg_info *dbgi, ir_node *block); 1228 1229 extern ir_op *op_ia32_Const; 1230 ir_op *get_op_ia32_Const(void); 1231 int is_ia32_Const(const ir_node *n); 1232 /** 1233 * construct Const node 1234 */ 1235 ir_node *new_bd_ia32_Const(dbg_info *dbgi, ir_node *block, ir_entity *symconst, int symconst_sign, int no_pic_adjust, long offset); 1236 1237 extern ir_op *op_ia32_Minus64Bit; 1238 ir_op *get_op_ia32_Minus64Bit(void); 1239 int is_ia32_Minus64Bit(const ir_node *n); 1240 /** 1241 * construct Minus64Bit node 1242 */ 1243 ir_node *new_bd_ia32_Minus64Bit(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1); 1244 1245 extern ir_op *op_ia32_Jmp; 1246 ir_op *get_op_ia32_Jmp(void); 1247 int is_ia32_Jmp(const ir_node *n); 1248 /** 1249 * construct Jmp node 1250 */ 1251 ir_node *new_bd_ia32_Jmp(dbg_info *dbgi, ir_node *block); 1252 1253 extern ir_op *op_ia32_FnstCW; 1254 ir_op *get_op_ia32_FnstCW(void); 1255 int is_ia32_FnstCW(const ir_node *n); 1256 /** 1257 * construct FnstCW node 1258 */ 1259 ir_node *new_bd_ia32_FnstCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *fpcw); 1260 1261 extern ir_op *op_ia32_Prefetch0; 1262 ir_op *get_op_ia32_Prefetch0(void); 1263 int is_ia32_Prefetch0(const ir_node *n); 1264 /** 1265 * construct Prefetch0 node 1266 */ 1267 ir_node *new_bd_ia32_Prefetch0(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 1268 1269 extern ir_op *op_ia32_OrMem; 1270 ir_op *get_op_ia32_OrMem(void); 1271 int is_ia32_OrMem(const ir_node *n); 1272 /** 1273 * construct OrMem node 1274 */ 1275 ir_node *new_bd_ia32_OrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1276 1277 extern ir_op *op_ia32_fldlg2; 1278 ir_op *get_op_ia32_fldlg2(void); 1279 int is_ia32_fldlg2(const ir_node *n); 1280 /** 1281 * construct fldlg2 node 1282 */ 1283 ir_node *new_bd_ia32_fldlg2(dbg_info *dbgi, ir_node *block); 1284 1285 extern ir_op *op_ia32_fld1; 1286 ir_op *get_op_ia32_fld1(void); 1287 int is_ia32_fld1(const ir_node *n); 1288 /** 1289 * construct fld1 node 1290 */ 1291 ir_node *new_bd_ia32_fld1(dbg_info *dbgi, ir_node *block); 1292 1293 extern ir_op *op_ia32_Conv_FP2I; 1294 ir_op *get_op_ia32_Conv_FP2I(void); 1295 int is_ia32_Conv_FP2I(const ir_node *n); 1296 /** 1297 * construct Conv_FP2I node 1298 */ 1299 ir_node *new_bd_ia32_Conv_FP2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1300 1301 extern ir_op *op_ia32_Popcnt; 1302 ir_op *get_op_ia32_Popcnt(void); 1303 int is_ia32_Popcnt(const ir_node *n); 1304 /** 1305 * construct Popcnt node 1306 */ 1307 ir_node *new_bd_ia32_Popcnt(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand); 1308 1309 extern ir_op *op_ia32_Ror; 1310 ir_op *get_op_ia32_Ror(void); 1311 int is_ia32_Ror(const ir_node *n); 1312 /** 1313 * construct Ror node 1314 */ 1315 ir_node *new_bd_ia32_Ror(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count); 1316 1317 extern ir_op *op_ia32_Shl; 1318 ir_op *get_op_ia32_Shl(void); 1319 int is_ia32_Shl(const ir_node *n); 1320 /** 1321 * construct Shl node 1322 */ 1323 ir_node *new_bd_ia32_Shl(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count); 1324 1325 extern ir_op *op_ia32_AndMem8Bit; 1326 ir_op *get_op_ia32_AndMem8Bit(void); 1327 int is_ia32_AndMem8Bit(const ir_node *n); 1328 /** 1329 * construct AndMem8Bit node 1330 */ 1331 ir_node *new_bd_ia32_AndMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1332 1333 extern ir_op *op_ia32_Add; 1334 ir_op *get_op_ia32_Add(void); 1335 int is_ia32_Add(const ir_node *n); 1336 /** 1337 * construct Add node 1338 */ 1339 ir_node *new_bd_ia32_Add(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 1340 1341 extern ir_op *op_ia32_SubSP; 1342 ir_op *get_op_ia32_SubSP(void); 1343 int is_ia32_SubSP(const ir_node *n); 1344 /** 1345 * construct SubSP node 1346 */ 1347 ir_node *new_bd_ia32_SubSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *size); 1348 1349 extern ir_op *op_ia32_PrefetchW; 1350 ir_op *get_op_ia32_PrefetchW(void); 1351 int is_ia32_PrefetchW(const ir_node *n); 1352 /** 1353 * construct PrefetchW node 1354 */ 1355 ir_node *new_bd_ia32_PrefetchW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 1356 1357 extern ir_op *op_ia32_Conv_I2I; 1358 ir_op *get_op_ia32_Conv_I2I(void); 1359 int is_ia32_Conv_I2I(const ir_node *n); 1360 /** 1361 * construct Conv_I2I node 1362 */ 1363 ir_node *new_bd_ia32_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *smaller_mode); 1364 1365 extern ir_op *op_ia32_fxch; 1366 ir_op *get_op_ia32_fxch(void); 1367 int is_ia32_fxch(const ir_node *n); 1368 /** 1369 * construct fxch node 1370 */ 1371 ir_node *new_bd_ia32_fxch(dbg_info *dbgi, ir_node *block); 1372 1373 extern ir_op *op_ia32_fchs; 1374 ir_op *get_op_ia32_fchs(void); 1375 int is_ia32_fchs(const ir_node *n); 1376 /** 1377 * construct fchs node 1378 */ 1379 ir_node *new_bd_ia32_fchs(dbg_info *dbgi, ir_node *block, ir_node *value); 1380 1381 extern ir_op *op_ia32_ShrD; 1382 ir_op *get_op_ia32_ShrD(void); 1383 int is_ia32_ShrD(const ir_node *n); 1384 /** 1385 * construct ShrD node 1386 */ 1387 ir_node *new_bd_ia32_ShrD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count); 1388 1389 extern ir_op *op_ia32_Unknown; 1390 ir_op *get_op_ia32_Unknown(void); 1391 int is_ia32_Unknown(const ir_node *n); 1392 /** 1393 * construct Unknown node 1394 */ 1395 ir_node *new_bd_ia32_Unknown(dbg_info *dbgi, ir_node *block); 1396 1397 extern ir_op *op_ia32_UD2; 1398 ir_op *get_op_ia32_UD2(void); 1399 int is_ia32_UD2(const ir_node *n); 1400 /** 1401 * construct UD2 node 1402 */ 1403 ir_node *new_bd_ia32_UD2(dbg_info *dbgi, ir_node *block, ir_node *mem); 1404 1405 extern ir_op *op_ia32_Cwtl; 1406 ir_op *get_op_ia32_Cwtl(void); 1407 int is_ia32_Cwtl(const ir_node *n); 1408 /** 1409 * construct Cwtl node 1410 */ 1411 ir_node *new_bd_ia32_Cwtl(dbg_info *dbgi, ir_node *block, ir_node *val); 1412 1413 extern ir_op *op_ia32_fabs; 1414 ir_op *get_op_ia32_fabs(void); 1415 int is_ia32_fabs(const ir_node *n); 1416 /** 1417 * construct fabs node 1418 */ 1419 ir_node *new_bd_ia32_fabs(dbg_info *dbgi, ir_node *block, ir_node *value); 1420 1421 extern ir_op *op_ia32_fldpi; 1422 ir_op *get_op_ia32_fldpi(void); 1423 int is_ia32_fldpi(const ir_node *n); 1424 /** 1425 * construct fldpi node 1426 */ 1427 ir_node *new_bd_ia32_fldpi(dbg_info *dbgi, ir_node *block); 1428 1429 extern ir_op *op_ia32_Leave; 1430 ir_op *get_op_ia32_Leave(void); 1431 int is_ia32_Leave(const ir_node *n); 1432 /** 1433 * construct Leave node 1434 */ 1435 ir_node *new_bd_ia32_Leave(dbg_info *dbgi, ir_node *block, ir_node *op0); 1436 1437 extern ir_op *op_ia32_Neg; 1438 ir_op *get_op_ia32_Neg(void); 1439 int is_ia32_Neg(const ir_node *n); 1440 /** 1441 * construct Neg node 1442 */ 1443 ir_node *new_bd_ia32_Neg(dbg_info *dbgi, ir_node *block, ir_node *val); 1444 1445 extern ir_op *op_ia32_IMul1OP; 1446 ir_op *get_op_ia32_IMul1OP(void); 1447 int is_ia32_IMul1OP(const ir_node *n); 1448 /** 1449 * construct IMul1OP node 1450 */ 1451 ir_node *new_bd_ia32_IMul1OP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 1452 1453 extern ir_op *op_ia32_PopMem; 1454 ir_op *get_op_ia32_PopMem(void); 1455 int is_ia32_PopMem(const ir_node *n); 1456 /** 1457 * construct PopMem node 1458 */ 1459 ir_node *new_bd_ia32_PopMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack); 1460 1461 extern ir_op *op_ia32_fld; 1462 ir_op *get_op_ia32_fld(void); 1463 int is_ia32_fld(const ir_node *n); 1464 /** 1465 * construct fld node 1466 */ 1467 ir_node *new_bd_ia32_fld(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_mode *load_mode); 1468 1469 extern ir_op *op_ia32_Dec; 1470 ir_op *get_op_ia32_Dec(void); 1471 int is_ia32_Dec(const ir_node *n); 1472 /** 1473 * construct Dec node 1474 */ 1475 ir_node *new_bd_ia32_Dec(dbg_info *dbgi, ir_node *block, ir_node *val); 1476 1477 extern ir_op *op_ia32_Pop; 1478 ir_op *get_op_ia32_Pop(void); 1479 int is_ia32_Pop(const ir_node *n); 1480 /** 1481 * construct Pop node 1482 */ 1483 ir_node *new_bd_ia32_Pop(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack); 1484 1485 extern ir_op *op_ia32_CopyEbpEsp; 1486 ir_op *get_op_ia32_CopyEbpEsp(void); 1487 int is_ia32_CopyEbpEsp(const ir_node *n); 1488 /** 1489 * construct CopyEbpEsp node 1490 */ 1491 ir_node *new_bd_ia32_CopyEbpEsp(dbg_info *dbgi, ir_node *block, ir_node *ebp); 1492 1493 extern ir_op *op_ia32_Not; 1494 ir_op *get_op_ia32_Not(void); 1495 int is_ia32_Not(const ir_node *n); 1496 /** 1497 * construct Not node 1498 */ 1499 ir_node *new_bd_ia32_Not(dbg_info *dbgi, ir_node *block, ir_node *val); 1500 1501 extern ir_op *op_ia32_NoReg_FP; 1502 ir_op *get_op_ia32_NoReg_FP(void); 1503 int is_ia32_NoReg_FP(const ir_node *n); 1504 /** 1505 * construct NoReg_FP node 1506 */ 1507 ir_node *new_bd_ia32_NoReg_FP(dbg_info *dbgi, ir_node *block); 1508 1509 extern ir_op *op_ia32_AndMem; 1510 ir_op *get_op_ia32_AndMem(void); 1511 int is_ia32_AndMem(const ir_node *n); 1512 /** 1513 * construct AndMem node 1514 */ 1515 ir_node *new_bd_ia32_AndMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1516 1517 extern ir_op *op_ia32_femms; 1518 ir_op *get_op_ia32_femms(void); 1519 int is_ia32_femms(const ir_node *n); 1520 /** 1521 * construct femms node 1522 */ 1523 ir_node *new_bd_ia32_femms(dbg_info *dbgi, ir_node *block); 1524 1525 extern ir_op *op_ia32_xStoreSimple; 1526 ir_op *get_op_ia32_xStoreSimple(void); 1527 int is_ia32_xStoreSimple(const ir_node *n); 1528 /** 1529 * construct xStoreSimple node 1530 */ 1531 ir_node *new_bd_ia32_xStoreSimple(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val); 1532 1533 extern ir_op *op_ia32_And; 1534 ir_op *get_op_ia32_And(void); 1535 int is_ia32_And(const ir_node *n); 1536 /** 1537 * construct And node 1538 */ 1539 ir_node *new_bd_ia32_And(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 1540 1541 extern ir_op *op_ia32_Jcc; 1542 ir_op *get_op_ia32_Jcc(void); 1543 int is_ia32_Jcc(const ir_node *n); 1544 /** 1545 * construct Jcc node 1546 */ 1547 ir_node *new_bd_ia32_Jcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, ia32_condition_code_t condition_code); 1548 1549 extern ir_op *op_ia32_Asm; 1550 ir_op *get_op_ia32_Asm(void); 1551 int is_ia32_Asm(const ir_node *n); 1552 /** 1553 * construct Asm node 1554 */ 1555 ir_node *new_bd_ia32_Asm(dbg_info *dbgi, ir_node *block, int arity, ir_node *in[], int n_res, ident *asm_text, const ia32_asm_reg_t *register_map); 1556 1557 extern ir_op *op_ia32_l_Sbb; 1558 ir_op *get_op_ia32_l_Sbb(void); 1559 int is_ia32_l_Sbb(const ir_node *n); 1560 /** 1561 * construct l_Sbb node 1562 */ 1563 ir_node *new_bd_ia32_l_Sbb(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, ir_mode *mode); 1564 1565 extern ir_op *op_ia32_Bsr; 1566 ir_op *get_op_ia32_Bsr(void); 1567 int is_ia32_Bsr(const ir_node *n); 1568 /** 1569 * construct Bsr node 1570 */ 1571 ir_node *new_bd_ia32_Bsr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand); 1572 1573 extern ir_op *op_ia32_Bswap16; 1574 ir_op *get_op_ia32_Bswap16(void); 1575 int is_ia32_Bswap16(const ir_node *n); 1576 /** 1577 * construct Bswap16 node 1578 */ 1579 ir_node *new_bd_ia32_Bswap16(dbg_info *dbgi, ir_node *block, ir_node *val); 1580 1581 extern ir_op *op_ia32_Inport; 1582 ir_op *get_op_ia32_Inport(void); 1583 int is_ia32_Inport(const ir_node *n); 1584 /** 1585 * construct Inport node 1586 */ 1587 ir_node *new_bd_ia32_Inport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *mem); 1588 1589 extern ir_op *op_ia32_SarMem; 1590 ir_op *get_op_ia32_SarMem(void); 1591 int is_ia32_SarMem(const ir_node *n); 1592 /** 1593 * construct SarMem node 1594 */ 1595 ir_node *new_bd_ia32_SarMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count); 1596 1597 extern ir_op *op_ia32_RepPrefix; 1598 ir_op *get_op_ia32_RepPrefix(void); 1599 int is_ia32_RepPrefix(const ir_node *n); 1600 /** 1601 * construct RepPrefix node 1602 */ 1603 ir_node *new_bd_ia32_RepPrefix(dbg_info *dbgi, ir_node *block); 1604 1605 extern ir_op *op_ia32_Adc; 1606 ir_op *get_op_ia32_Adc(void); 1607 int is_ia32_Adc(const ir_node *n); 1608 /** 1609 * construct Adc node 1610 */ 1611 ir_node *new_bd_ia32_Adc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *eflags); 1612 1613 extern ir_op *op_ia32_l_Mul; 1614 ir_op *get_op_ia32_l_Mul(void); 1615 int is_ia32_l_Mul(const ir_node *n); 1616 /** 1617 * construct l_Mul node 1618 */ 1619 ir_node *new_bd_ia32_l_Mul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right); 1620 1621 extern ir_op *op_ia32_xAndNot; 1622 ir_op *get_op_ia32_xAndNot(void); 1623 int is_ia32_xAndNot(const ir_node *n); 1624 /** 1625 * construct xAndNot node 1626 */ 1627 ir_node *new_bd_ia32_xAndNot(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right); 1628 1629 extern ir_op *op_ia32_Load; 1630 ir_op *get_op_ia32_Load(void); 1631 int is_ia32_Load(const ir_node *n); 1632 /** 1633 * construct Load node 1634 */ 1635 ir_node *new_bd_ia32_Load(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 1636 1637 extern ir_op *op_ia32_Prefetch; 1638 ir_op *get_op_ia32_Prefetch(void); 1639 int is_ia32_Prefetch(const ir_node *n); 1640 /** 1641 * construct Prefetch node 1642 */ 1643 ir_node *new_bd_ia32_Prefetch(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); 1644 1645 1646 1647 enum n_ia32_FldCW { 1648 n_ia32_FldCW_base = 0, 1649 n_ia32_FldCW_index = 1, 1650 n_ia32_FldCW_mem = 2, 1651 }; 1652 1653 enum pn_ia32_fadd { 1654 pn_ia32_fadd_res = 0, 1655 pn_ia32_fadd_dummy = 1, 1656 pn_ia32_fadd_M = 2, 1657 }; 1658 1659 enum n_ia32_fadd { 1660 n_ia32_fadd_base = 0, 1661 n_ia32_fadd_index = 1, 1662 n_ia32_fadd_mem = 2, 1663 n_ia32_fadd_left = 3, 1664 n_ia32_fadd_right = 4, 1665 n_ia32_fadd_fpcw = 5, 1666 }; 1667 1668 enum n_ia32_ShrMem { 1669 n_ia32_ShrMem_base = 0, 1670 n_ia32_ShrMem_index = 1, 1671 n_ia32_ShrMem_mem = 2, 1672 n_ia32_ShrMem_count = 3, 1673 }; 1674 1675 enum n_ia32_CvtSI2SS { 1676 n_ia32_CvtSI2SS_base = 0, 1677 n_ia32_CvtSI2SS_index = 1, 1678 n_ia32_CvtSI2SS_mem = 2, 1679 n_ia32_CvtSI2SS_val = 3, 1680 }; 1681 1682 enum pn_ia32_Bsf { 1683 pn_ia32_Bsf_res = 0, 1684 pn_ia32_Bsf_flags = 1, 1685 pn_ia32_Bsf_M = 2, 1686 }; 1687 1688 enum n_ia32_Bsf { 1689 n_ia32_Bsf_base = 0, 1690 n_ia32_Bsf_index = 1, 1691 n_ia32_Bsf_mem = 2, 1692 n_ia32_Bsf_operand = 3, 1693 }; 1694 1695 enum pn_ia32_ShlD { 1696 pn_ia32_ShlD_res = 0, 1697 pn_ia32_ShlD_flags = 1, 1698 }; 1699 1700 enum n_ia32_ShlD { 1701 n_ia32_ShlD_val_high = 0, 1702 n_ia32_ShlD_val_low = 1, 1703 n_ia32_ShlD_count = 2, 1704 }; 1705 1706 enum pn_ia32_PopEbp { 1707 pn_ia32_PopEbp_res = 0, 1708 pn_ia32_PopEbp_M = 1, 1709 pn_ia32_PopEbp_unused = 2, 1710 pn_ia32_PopEbp_stack = 3, 1711 }; 1712 1713 enum n_ia32_PopEbp { 1714 n_ia32_PopEbp_mem = 0, 1715 n_ia32_PopEbp_stack = 1, 1716 }; 1717 1718 enum pn_ia32_Inc { 1719 pn_ia32_Inc_res = 0, 1720 pn_ia32_Inc_flags = 1, 1721 }; 1722 1723 enum n_ia32_Inc { 1724 n_ia32_Inc_val = 0, 1725 }; 1726 1727 enum pn_ia32_xStore { 1728 pn_ia32_xStore_M = 0, 1729 pn_ia32_xStore_X_regular = 1, 1730 pn_ia32_xStore_X_except = 2, 1731 }; 1732 1733 enum n_ia32_xStore { 1734 n_ia32_xStore_base = 0, 1735 n_ia32_xStore_index = 1, 1736 n_ia32_xStore_mem = 2, 1737 n_ia32_xStore_val = 3, 1738 }; 1739 1740 enum pn_ia32_xxLoad { 1741 pn_ia32_xxLoad_res = 0, 1742 pn_ia32_xxLoad_M = 1, 1743 pn_ia32_xxLoad_X_regular = 2, 1744 pn_ia32_xxLoad_X_except = 3, 1745 }; 1746 1747 enum n_ia32_xxLoad { 1748 n_ia32_xxLoad_base = 0, 1749 n_ia32_xxLoad_index = 1, 1750 n_ia32_xxLoad_mem = 2, 1751 }; 1752 1753 enum pn_ia32_xAnd { 1754 pn_ia32_xAnd_res = 0, 1755 pn_ia32_xAnd_flags = 1, 1756 pn_ia32_xAnd_M = 2, 1757 }; 1758 1759 enum n_ia32_xAnd { 1760 n_ia32_xAnd_base = 0, 1761 n_ia32_xAnd_index = 1, 1762 n_ia32_xAnd_mem = 2, 1763 n_ia32_xAnd_left = 3, 1764 n_ia32_xAnd_right = 4, 1765 }; 1766 1767 enum pn_ia32_xAdd { 1768 pn_ia32_xAdd_res = 0, 1769 pn_ia32_xAdd_flags = 1, 1770 pn_ia32_xAdd_M = 2, 1771 }; 1772 1773 enum n_ia32_xAdd { 1774 n_ia32_xAdd_base = 0, 1775 n_ia32_xAdd_index = 1, 1776 n_ia32_xAdd_mem = 2, 1777 n_ia32_xAdd_left = 3, 1778 n_ia32_xAdd_right = 4, 1779 }; 1780 1781 enum pn_ia32_xxStore { 1782 pn_ia32_xxStore_M = 0, 1783 pn_ia32_xxStore_X_regular = 1, 1784 pn_ia32_xxStore_X_except = 2, 1785 }; 1786 1787 enum n_ia32_xxStore { 1788 n_ia32_xxStore_base = 0, 1789 n_ia32_xxStore_index = 1, 1790 n_ia32_xxStore_mem = 2, 1791 n_ia32_xxStore_val = 3, 1792 }; 1793 1794 enum pn_ia32_Call { 1795 pn_ia32_Call_stack = 0, 1796 pn_ia32_Call_fpcw = 1, 1797 pn_ia32_Call_M = 2, 1798 pn_ia32_Call_eax = 3, 1799 pn_ia32_Call_ecx = 4, 1800 pn_ia32_Call_edx = 5, 1801 pn_ia32_Call_st0 = 6, 1802 pn_ia32_Call_st1 = 7, 1803 pn_ia32_Call_st2 = 8, 1804 pn_ia32_Call_st3 = 9, 1805 pn_ia32_Call_st4 = 10, 1806 pn_ia32_Call_st5 = 11, 1807 pn_ia32_Call_st6 = 12, 1808 pn_ia32_Call_st7 = 13, 1809 pn_ia32_Call_xmm0 = 14, 1810 pn_ia32_Call_xmm1 = 15, 1811 pn_ia32_Call_xmm2 = 16, 1812 pn_ia32_Call_xmm3 = 17, 1813 pn_ia32_Call_xmm4 = 18, 1814 pn_ia32_Call_xmm5 = 19, 1815 pn_ia32_Call_xmm6 = 20, 1816 pn_ia32_Call_xmm7 = 21, 1817 pn_ia32_Call_X_regular = 22, 1818 pn_ia32_Call_X_except = 23, 1819 }; 1820 1821 enum n_ia32_Call { 1822 n_ia32_Call_base = 0, 1823 n_ia32_Call_index = 1, 1824 n_ia32_Call_mem = 2, 1825 n_ia32_Call_addr = 3, 1826 n_ia32_Call_stack = 4, 1827 n_ia32_Call_fpcw = 5, 1828 n_ia32_Call_eax = 6, 1829 n_ia32_Call_ecx = 7, 1830 n_ia32_Call_edx = 8, 1831 }; 1832 1833 enum n_ia32_FnstCWNOP { 1834 n_ia32_FnstCWNOP_fpcw = 0, 1835 }; 1836 1837 enum n_ia32_XorMem8Bit { 1838 n_ia32_XorMem8Bit_base = 0, 1839 n_ia32_XorMem8Bit_index = 1, 1840 n_ia32_XorMem8Bit_mem = 2, 1841 n_ia32_XorMem8Bit_val = 3, 1842 }; 1843 1844 enum pn_ia32_fldl2t { 1845 pn_ia32_fldl2t_res = 0, 1846 }; 1847 1848 enum pn_ia32_fisttp { 1849 pn_ia32_fisttp_res = 0, 1850 pn_ia32_fisttp_M = 1, 1851 pn_ia32_fisttp_X_regular = 2, 1852 pn_ia32_fisttp_X_except = 3, 1853 }; 1854 1855 enum n_ia32_fisttp { 1856 n_ia32_fisttp_base = 0, 1857 n_ia32_fisttp_index = 1, 1858 n_ia32_fisttp_mem = 2, 1859 n_ia32_fisttp_val = 3, 1860 }; 1861 1862 enum n_ia32_DecMem { 1863 n_ia32_DecMem_base = 0, 1864 n_ia32_DecMem_index = 1, 1865 n_ia32_DecMem_mem = 2, 1866 }; 1867 1868 enum pn_ia32_xLoad { 1869 pn_ia32_xLoad_res = 0, 1870 pn_ia32_xLoad_unused = 1, 1871 pn_ia32_xLoad_M = 2, 1872 pn_ia32_xLoad_X_regular = 3, 1873 pn_ia32_xLoad_X_except = 4, 1874 }; 1875 1876 enum n_ia32_xLoad { 1877 n_ia32_xLoad_base = 0, 1878 n_ia32_xLoad_index = 1, 1879 n_ia32_xLoad_mem = 2, 1880 }; 1881 1882 enum pn_ia32_l_FloattoLL { 1883 pn_ia32_l_FloattoLL_res_high = 0, 1884 pn_ia32_l_FloattoLL_res_low = 1, 1885 }; 1886 1887 enum n_ia32_l_FloattoLL { 1888 n_ia32_l_FloattoLL_val = 0, 1889 }; 1890 1891 enum n_ia32_CvtSI2SD { 1892 n_ia32_CvtSI2SD_base = 0, 1893 n_ia32_CvtSI2SD_index = 1, 1894 n_ia32_CvtSI2SD_mem = 2, 1895 n_ia32_CvtSI2SD_val = 3, 1896 }; 1897 1898 enum n_ia32_XorMem { 1899 n_ia32_XorMem_base = 0, 1900 n_ia32_XorMem_index = 1, 1901 n_ia32_XorMem_mem = 2, 1902 n_ia32_XorMem_val = 3, 1903 }; 1904 1905 enum pn_ia32_CopyB { 1906 pn_ia32_CopyB_dest = 0, 1907 pn_ia32_CopyB_source = 1, 1908 pn_ia32_CopyB_count = 2, 1909 pn_ia32_CopyB_M = 3, 1910 pn_ia32_CopyB_X_regular = 4, 1911 pn_ia32_CopyB_X_except = 5, 1912 }; 1913 1914 enum n_ia32_CopyB { 1915 n_ia32_CopyB_dest = 0, 1916 n_ia32_CopyB_source = 1, 1917 n_ia32_CopyB_count = 2, 1918 n_ia32_CopyB_mem = 3, 1919 }; 1920 1921 enum pn_ia32_Xor0 { 1922 pn_ia32_Xor0_res = 0, 1923 pn_ia32_Xor0_flags = 1, 1924 }; 1925 1926 enum pn_ia32_Sar { 1927 pn_ia32_Sar_res = 0, 1928 pn_ia32_Sar_flags = 1, 1929 }; 1930 1931 enum n_ia32_Sar { 1932 n_ia32_Sar_val = 0, 1933 n_ia32_Sar_count = 1, 1934 }; 1935 1936 enum pn_ia32_Div { 1937 pn_ia32_Div_div_res = 0, 1938 pn_ia32_Div_flags = 1, 1939 pn_ia32_Div_M = 2, 1940 pn_ia32_Div_mod_res = 3, 1941 pn_ia32_Div_X_regular = 4, 1942 pn_ia32_Div_X_except = 5, 1943 }; 1944 1945 enum n_ia32_Div { 1946 n_ia32_Div_base = 0, 1947 n_ia32_Div_index = 1, 1948 n_ia32_Div_mem = 2, 1949 n_ia32_Div_divisor = 3, 1950 n_ia32_Div_dividend_low = 4, 1951 n_ia32_Div_dividend_high = 5, 1952 }; 1953 1954 enum pn_ia32_Fucomi { 1955 pn_ia32_Fucomi_flags = 0, 1956 }; 1957 1958 enum n_ia32_Fucomi { 1959 n_ia32_Fucomi_left = 0, 1960 n_ia32_Fucomi_right = 1, 1961 }; 1962 1963 enum pn_ia32_fldl2e { 1964 pn_ia32_fldl2e_res = 0, 1965 }; 1966 1967 enum pn_ia32_Enter { 1968 pn_ia32_Enter_frame = 0, 1969 pn_ia32_Enter_stack = 1, 1970 pn_ia32_Enter_M = 2, 1971 }; 1972 1973 enum pn_ia32_fmul { 1974 pn_ia32_fmul_res = 0, 1975 pn_ia32_fmul_dummy = 1, 1976 pn_ia32_fmul_M = 2, 1977 }; 1978 1979 enum n_ia32_fmul { 1980 n_ia32_fmul_base = 0, 1981 n_ia32_fmul_index = 1, 1982 n_ia32_fmul_mem = 2, 1983 n_ia32_fmul_left = 3, 1984 n_ia32_fmul_right = 4, 1985 n_ia32_fmul_fpcw = 5, 1986 }; 1987 1988 enum pn_ia32_l_IMul { 1989 pn_ia32_l_IMul_res_low = 0, 1990 pn_ia32_l_IMul_flags = 1, 1991 pn_ia32_l_IMul_M = 2, 1992 pn_ia32_l_IMul_res_high = 3, 1993 }; 1994 1995 enum n_ia32_l_IMul { 1996 n_ia32_l_IMul_left = 0, 1997 n_ia32_l_IMul_right = 1, 1998 }; 1999 2000 enum pn_ia32_xMax { 2001 pn_ia32_xMax_res = 0, 2002 pn_ia32_xMax_flags = 1, 2003 pn_ia32_xMax_M = 2, 2004 }; 2005 2006 enum n_ia32_xMax { 2007 n_ia32_xMax_base = 0, 2008 n_ia32_xMax_index = 1, 2009 n_ia32_xMax_mem = 2, 2010 n_ia32_xMax_left = 3, 2011 n_ia32_xMax_right = 4, 2012 }; 2013 2014 enum n_ia32_OrMem8Bit { 2015 n_ia32_OrMem8Bit_base = 0, 2016 n_ia32_OrMem8Bit_index = 1, 2017 n_ia32_OrMem8Bit_mem = 2, 2018 n_ia32_OrMem8Bit_val = 3, 2019 }; 2020 2021 enum pn_ia32_Prefetch1 { 2022 pn_ia32_Prefetch1_M = 0, 2023 }; 2024 2025 enum n_ia32_Prefetch1 { 2026 n_ia32_Prefetch1_base = 0, 2027 n_ia32_Prefetch1_index = 1, 2028 n_ia32_Prefetch1_mem = 2, 2029 }; 2030 2031 enum pn_ia32_fsub { 2032 pn_ia32_fsub_res = 0, 2033 pn_ia32_fsub_dummy = 1, 2034 pn_ia32_fsub_M = 2, 2035 }; 2036 2037 enum n_ia32_fsub { 2038 n_ia32_fsub_base = 0, 2039 n_ia32_fsub_index = 1, 2040 n_ia32_fsub_mem = 2, 2041 n_ia32_fsub_minuend = 3, 2042 n_ia32_fsub_subtrahend = 4, 2043 n_ia32_fsub_fpcw = 5, 2044 }; 2045 2046 enum n_ia32_Lea { 2047 n_ia32_Lea_base = 0, 2048 n_ia32_Lea_index = 1, 2049 }; 2050 2051 enum pn_ia32_FtstFnstsw { 2052 pn_ia32_FtstFnstsw_flags = 0, 2053 }; 2054 2055 enum n_ia32_FtstFnstsw { 2056 n_ia32_FtstFnstsw_left = 0, 2057 }; 2058 2059 enum n_ia32_NotMem { 2060 n_ia32_NotMem_base = 0, 2061 n_ia32_NotMem_index = 1, 2062 n_ia32_NotMem_mem = 2, 2063 }; 2064 2065 enum pn_ia32_Sbb0 { 2066 pn_ia32_Sbb0_res = 0, 2067 pn_ia32_Sbb0_flags = 1, 2068 }; 2069 2070 enum n_ia32_Bt { 2071 n_ia32_Bt_left = 0, 2072 n_ia32_Bt_right = 1, 2073 }; 2074 2075 enum pn_ia32_Or { 2076 pn_ia32_Or_res = 0, 2077 pn_ia32_Or_flags = 1, 2078 pn_ia32_Or_M = 2, 2079 }; 2080 2081 enum n_ia32_Or { 2082 n_ia32_Or_base = 0, 2083 n_ia32_Or_index = 1, 2084 n_ia32_Or_mem = 2, 2085 n_ia32_Or_left = 3, 2086 n_ia32_Or_right = 4, 2087 }; 2088 2089 enum pn_ia32_Xor { 2090 pn_ia32_Xor_res = 0, 2091 pn_ia32_Xor_flags = 1, 2092 pn_ia32_Xor_M = 2, 2093 }; 2094 2095 enum n_ia32_Xor { 2096 n_ia32_Xor_base = 0, 2097 n_ia32_Xor_index = 1, 2098 n_ia32_Xor_mem = 2, 2099 n_ia32_Xor_left = 3, 2100 n_ia32_Xor_right = 4, 2101 }; 2102 2103 enum pn_ia32_CopyB_i { 2104 pn_ia32_CopyB_i_dest = 0, 2105 pn_ia32_CopyB_i_source = 1, 2106 pn_ia32_CopyB_i_M = 2, 2107 pn_ia32_CopyB_i_X_regular = 3, 2108 pn_ia32_CopyB_i_X_except = 4, 2109 }; 2110 2111 enum n_ia32_CopyB_i { 2112 n_ia32_CopyB_i_dest = 0, 2113 n_ia32_CopyB_i_source = 1, 2114 n_ia32_CopyB_i_mem = 2, 2115 }; 2116 2117 enum n_ia32_IncMem { 2118 n_ia32_IncMem_base = 0, 2119 n_ia32_IncMem_index = 1, 2120 n_ia32_IncMem_mem = 2, 2121 }; 2122 2123 enum n_ia32_Breakpoint { 2124 n_ia32_Breakpoint_mem = 0, 2125 }; 2126 2127 enum pn_ia32_ClimbFrame { 2128 pn_ia32_ClimbFrame_res = 0, 2129 }; 2130 2131 enum n_ia32_ClimbFrame { 2132 n_ia32_ClimbFrame_frame = 0, 2133 n_ia32_ClimbFrame_cnt = 1, 2134 n_ia32_ClimbFrame_tmp = 2, 2135 }; 2136 2137 enum n_ia32_SubMem { 2138 n_ia32_SubMem_base = 0, 2139 n_ia32_SubMem_index = 1, 2140 n_ia32_SubMem_mem = 2, 2141 n_ia32_SubMem_subtrahend = 3, 2142 }; 2143 2144 enum n_ia32_AddMem { 2145 n_ia32_AddMem_base = 0, 2146 n_ia32_AddMem_index = 1, 2147 n_ia32_AddMem_mem = 2, 2148 n_ia32_AddMem_val = 3, 2149 }; 2150 2151 enum n_ia32_ShlMem { 2152 n_ia32_ShlMem_base = 0, 2153 n_ia32_ShlMem_index = 1, 2154 n_ia32_ShlMem_mem = 2, 2155 n_ia32_ShlMem_count = 3, 2156 }; 2157 2158 enum pn_ia32_fdiv { 2159 pn_ia32_fdiv_res = 0, 2160 pn_ia32_fdiv_dummy = 1, 2161 pn_ia32_fdiv_M = 2, 2162 }; 2163 2164 enum n_ia32_fdiv { 2165 n_ia32_fdiv_base = 0, 2166 n_ia32_fdiv_index = 1, 2167 n_ia32_fdiv_mem = 2, 2168 n_ia32_fdiv_dividend = 3, 2169 n_ia32_fdiv_divisor = 4, 2170 n_ia32_fdiv_fpcw = 5, 2171 }; 2172 2173 enum n_ia32_Outport { 2174 n_ia32_Outport_port = 0, 2175 n_ia32_Outport_value = 1, 2176 n_ia32_Outport_mem = 2, 2177 }; 2178 2179 enum pn_ia32_xMin { 2180 pn_ia32_xMin_res = 0, 2181 pn_ia32_xMin_flags = 1, 2182 pn_ia32_xMin_M = 2, 2183 }; 2184 2185 enum n_ia32_xMin { 2186 n_ia32_xMin_base = 0, 2187 n_ia32_xMin_index = 1, 2188 n_ia32_xMin_mem = 2, 2189 n_ia32_xMin_left = 3, 2190 n_ia32_xMin_right = 4, 2191 }; 2192 2193 enum pn_ia32_fist { 2194 pn_ia32_fist_dummy = 0, 2195 pn_ia32_fist_M = 1, 2196 pn_ia32_fist_X_regular = 2, 2197 pn_ia32_fist_X_except = 3, 2198 }; 2199 2200 enum n_ia32_fist { 2201 n_ia32_fist_base = 0, 2202 n_ia32_fist_index = 1, 2203 n_ia32_fist_mem = 2, 2204 n_ia32_fist_val = 3, 2205 n_ia32_fist_fpcw = 4, 2206 }; 2207 2208 enum pn_ia32_xXor { 2209 pn_ia32_xXor_res = 0, 2210 pn_ia32_xXor_flags = 1, 2211 pn_ia32_xXor_M = 2, 2212 }; 2213 2214 enum n_ia32_xXor { 2215 n_ia32_xXor_base = 0, 2216 n_ia32_xXor_index = 1, 2217 n_ia32_xXor_mem = 2, 2218 n_ia32_xXor_left = 3, 2219 n_ia32_xXor_right = 4, 2220 }; 2221 2222 enum pn_ia32_IJmp { 2223 pn_ia32_IJmp_jmp = 0, 2224 pn_ia32_IJmp_flags = 1, 2225 pn_ia32_IJmp_M = 2, 2226 }; 2227 2228 enum n_ia32_IJmp { 2229 n_ia32_IJmp_base = 0, 2230 n_ia32_IJmp_index = 1, 2231 n_ia32_IJmp_mem = 2, 2232 n_ia32_IJmp_target = 3, 2233 }; 2234 2235 enum n_ia32_NegMem { 2236 n_ia32_NegMem_base = 0, 2237 n_ia32_NegMem_index = 1, 2238 n_ia32_NegMem_mem = 2, 2239 }; 2240 2241 enum pn_ia32_CMovcc { 2242 pn_ia32_CMovcc_res = 0, 2243 pn_ia32_CMovcc_flags = 1, 2244 pn_ia32_CMovcc_M = 2, 2245 }; 2246 2247 enum n_ia32_CMovcc { 2248 n_ia32_CMovcc_base = 0, 2249 n_ia32_CMovcc_index = 1, 2250 n_ia32_CMovcc_mem = 2, 2251 n_ia32_CMovcc_val_false = 3, 2252 n_ia32_CMovcc_val_true = 4, 2253 n_ia32_CMovcc_eflags = 5, 2254 }; 2255 2256 enum pn_ia32_Mul { 2257 pn_ia32_Mul_res_low = 0, 2258 pn_ia32_Mul_flags = 1, 2259 pn_ia32_Mul_M = 2, 2260 pn_ia32_Mul_res_high = 3, 2261 }; 2262 2263 enum n_ia32_Mul { 2264 n_ia32_Mul_base = 0, 2265 n_ia32_Mul_index = 1, 2266 n_ia32_Mul_mem = 2, 2267 n_ia32_Mul_left = 3, 2268 n_ia32_Mul_right = 4, 2269 }; 2270 2271 enum pn_ia32_Sahf { 2272 pn_ia32_Sahf_flags = 0, 2273 }; 2274 2275 enum n_ia32_Sahf { 2276 n_ia32_Sahf_val = 0, 2277 }; 2278 2279 enum n_ia32_SubMem8Bit { 2280 n_ia32_SubMem8Bit_base = 0, 2281 n_ia32_SubMem8Bit_index = 1, 2282 n_ia32_SubMem8Bit_mem = 2, 2283 n_ia32_SubMem8Bit_subtrahend = 3, 2284 }; 2285 2286 enum n_ia32_AddMem8Bit { 2287 n_ia32_AddMem8Bit_base = 0, 2288 n_ia32_AddMem8Bit_index = 1, 2289 n_ia32_AddMem8Bit_mem = 2, 2290 n_ia32_AddMem8Bit_val = 3, 2291 }; 2292 2293 enum pn_ia32_fst { 2294 pn_ia32_fst_M = 0, 2295 pn_ia32_fst_X_regular = 1, 2296 pn_ia32_fst_X_except = 2, 2297 }; 2298 2299 enum n_ia32_fst { 2300 n_ia32_fst_base = 0, 2301 n_ia32_fst_index = 1, 2302 n_ia32_fst_mem = 2, 2303 n_ia32_fst_val = 3, 2304 }; 2305 2306 enum pn_ia32_FucomppFnstsw { 2307 pn_ia32_FucomppFnstsw_flags = 0, 2308 }; 2309 2310 enum n_ia32_FucomppFnstsw { 2311 n_ia32_FucomppFnstsw_left = 0, 2312 n_ia32_FucomppFnstsw_right = 1, 2313 }; 2314 2315 enum n_ia32_RorMem { 2316 n_ia32_RorMem_base = 0, 2317 n_ia32_RorMem_index = 1, 2318 n_ia32_RorMem_mem = 2, 2319 n_ia32_RorMem_count = 3, 2320 }; 2321 2322 enum pn_ia32_fild { 2323 pn_ia32_fild_res = 0, 2324 pn_ia32_fild_unused = 1, 2325 pn_ia32_fild_M = 2, 2326 }; 2327 2328 enum n_ia32_fild { 2329 n_ia32_fild_base = 0, 2330 n_ia32_fild_index = 1, 2331 n_ia32_fild_mem = 2, 2332 }; 2333 2334 enum pn_ia32_xOr { 2335 pn_ia32_xOr_res = 0, 2336 pn_ia32_xOr_flags = 1, 2337 pn_ia32_xOr_M = 2, 2338 }; 2339 2340 enum n_ia32_xOr { 2341 n_ia32_xOr_base = 0, 2342 n_ia32_xOr_index = 1, 2343 n_ia32_xOr_mem = 2, 2344 n_ia32_xOr_left = 3, 2345 n_ia32_xOr_right = 4, 2346 }; 2347 2348 enum pn_ia32_Conv_I2I8Bit { 2349 pn_ia32_Conv_I2I8Bit_res = 0, 2350 pn_ia32_Conv_I2I8Bit_flags = 1, 2351 pn_ia32_Conv_I2I8Bit_M = 2, 2352 pn_ia32_Conv_I2I8Bit_X_regular = 3, 2353 pn_ia32_Conv_I2I8Bit_X_except = 4, 2354 }; 2355 2356 enum n_ia32_Conv_I2I8Bit { 2357 n_ia32_Conv_I2I8Bit_base = 0, 2358 n_ia32_Conv_I2I8Bit_index = 1, 2359 n_ia32_Conv_I2I8Bit_mem = 2, 2360 n_ia32_Conv_I2I8Bit_val = 3, 2361 }; 2362 2363 enum pn_ia32_Store { 2364 pn_ia32_Store_M = 0, 2365 pn_ia32_Store_X_regular = 1, 2366 pn_ia32_Store_X_except = 2, 2367 }; 2368 2369 enum n_ia32_Store { 2370 n_ia32_Store_base = 0, 2371 n_ia32_Store_index = 1, 2372 n_ia32_Store_mem = 2, 2373 n_ia32_Store_val = 3, 2374 }; 2375 2376 enum pn_ia32_fldln2 { 2377 pn_ia32_fldln2_res = 0, 2378 }; 2379 2380 enum n_ia32_SwitchJmp { 2381 n_ia32_SwitchJmp_base = 0, 2382 n_ia32_SwitchJmp_index = 1, 2383 }; 2384 2385 enum pn_ia32_IMul { 2386 pn_ia32_IMul_res = 0, 2387 pn_ia32_IMul_flags = 1, 2388 pn_ia32_IMul_M = 2, 2389 }; 2390 2391 enum n_ia32_IMul { 2392 n_ia32_IMul_base = 0, 2393 n_ia32_IMul_index = 1, 2394 n_ia32_IMul_mem = 2, 2395 n_ia32_IMul_left = 3, 2396 n_ia32_IMul_right = 4, 2397 }; 2398 2399 enum pn_ia32_Ucomi { 2400 pn_ia32_Ucomi_flags = 0, 2401 }; 2402 2403 enum n_ia32_Ucomi { 2404 n_ia32_Ucomi_base = 0, 2405 n_ia32_Ucomi_index = 1, 2406 n_ia32_Ucomi_mem = 2, 2407 n_ia32_Ucomi_left = 3, 2408 n_ia32_Ucomi_right = 4, 2409 }; 2410 2411 enum pn_ia32_fldz { 2412 pn_ia32_fldz_res = 0, 2413 }; 2414 2415 enum pn_ia32_Store8Bit { 2416 pn_ia32_Store8Bit_M = 0, 2417 pn_ia32_Store8Bit_X_regular = 1, 2418 pn_ia32_Store8Bit_X_except = 2, 2419 }; 2420 2421 enum n_ia32_Store8Bit { 2422 n_ia32_Store8Bit_base = 0, 2423 n_ia32_Store8Bit_index = 1, 2424 n_ia32_Store8Bit_mem = 2, 2425 n_ia32_Store8Bit_val = 3, 2426 }; 2427 2428 enum n_ia32_l_Sub { 2429 n_ia32_l_Sub_minuend = 0, 2430 n_ia32_l_Sub_subtrahend = 1, 2431 }; 2432 2433 enum pn_ia32_Sbb { 2434 pn_ia32_Sbb_res = 0, 2435 pn_ia32_Sbb_flags = 1, 2436 pn_ia32_Sbb_M = 2, 2437 }; 2438 2439 enum n_ia32_Sbb { 2440 n_ia32_Sbb_base = 0, 2441 n_ia32_Sbb_index = 1, 2442 n_ia32_Sbb_mem = 2, 2443 n_ia32_Sbb_minuend = 3, 2444 n_ia32_Sbb_subtrahend = 4, 2445 n_ia32_Sbb_eflags = 5, 2446 }; 2447 2448 enum pn_ia32_FucomFnstsw { 2449 pn_ia32_FucomFnstsw_flags = 0, 2450 }; 2451 2452 enum n_ia32_FucomFnstsw { 2453 n_ia32_FucomFnstsw_left = 0, 2454 n_ia32_FucomFnstsw_right = 1, 2455 }; 2456 2457 enum pn_ia32_xMul { 2458 pn_ia32_xMul_res = 0, 2459 pn_ia32_xMul_flags = 1, 2460 pn_ia32_xMul_M = 2, 2461 }; 2462 2463 enum n_ia32_xMul { 2464 n_ia32_xMul_base = 0, 2465 n_ia32_xMul_index = 1, 2466 n_ia32_xMul_mem = 2, 2467 n_ia32_xMul_left = 3, 2468 n_ia32_xMul_right = 4, 2469 }; 2470 2471 enum pn_ia32_Push { 2472 pn_ia32_Push_stack = 0, 2473 pn_ia32_Push_M = 1, 2474 }; 2475 2476 enum n_ia32_Push { 2477 n_ia32_Push_base = 0, 2478 n_ia32_Push_index = 1, 2479 n_ia32_Push_mem = 2, 2480 n_ia32_Push_val = 3, 2481 n_ia32_Push_stack = 4, 2482 }; 2483 2484 enum pn_ia32_Cmp { 2485 pn_ia32_Cmp_eflags = 0, 2486 pn_ia32_Cmp_unused = 1, 2487 pn_ia32_Cmp_M = 2, 2488 }; 2489 2490 enum n_ia32_Cmp { 2491 n_ia32_Cmp_base = 0, 2492 n_ia32_Cmp_index = 1, 2493 n_ia32_Cmp_mem = 2, 2494 n_ia32_Cmp_left = 3, 2495 n_ia32_Cmp_right = 4, 2496 }; 2497 2498 enum pn_ia32_xSub { 2499 pn_ia32_xSub_res = 0, 2500 pn_ia32_xSub_flags = 1, 2501 pn_ia32_xSub_M = 2, 2502 }; 2503 2504 enum n_ia32_xSub { 2505 n_ia32_xSub_base = 0, 2506 n_ia32_xSub_index = 1, 2507 n_ia32_xSub_mem = 2, 2508 n_ia32_xSub_minuend = 3, 2509 n_ia32_xSub_subtrahend = 4, 2510 }; 2511 2512 enum n_ia32_Cltd { 2513 n_ia32_Cltd_val = 0, 2514 n_ia32_Cltd_clobbered = 1, 2515 }; 2516 2517 enum pn_ia32_PushEax { 2518 pn_ia32_PushEax_stack = 0, 2519 }; 2520 2521 enum n_ia32_PushEax { 2522 n_ia32_PushEax_stack = 0, 2523 }; 2524 2525 enum pn_ia32_XorHighLow { 2526 pn_ia32_XorHighLow_res = 0, 2527 pn_ia32_XorHighLow_flags = 1, 2528 }; 2529 2530 enum n_ia32_XorHighLow { 2531 n_ia32_XorHighLow_value = 0, 2532 }; 2533 2534 enum pn_ia32_Rol { 2535 pn_ia32_Rol_res = 0, 2536 pn_ia32_Rol_flags = 1, 2537 }; 2538 2539 enum n_ia32_Rol { 2540 n_ia32_Rol_val = 0, 2541 n_ia32_Rol_count = 1, 2542 }; 2543 2544 enum pn_ia32_Cmp8Bit { 2545 pn_ia32_Cmp8Bit_eflags = 0, 2546 pn_ia32_Cmp8Bit_unused = 1, 2547 pn_ia32_Cmp8Bit_M = 2, 2548 }; 2549 2550 enum n_ia32_Cmp8Bit { 2551 n_ia32_Cmp8Bit_base = 0, 2552 n_ia32_Cmp8Bit_index = 1, 2553 n_ia32_Cmp8Bit_mem = 2, 2554 n_ia32_Cmp8Bit_left = 3, 2555 n_ia32_Cmp8Bit_right = 4, 2556 }; 2557 2558 enum pn_ia32_xDiv { 2559 pn_ia32_xDiv_res = 0, 2560 pn_ia32_xDiv_flags = 1, 2561 pn_ia32_xDiv_M = 2, 2562 }; 2563 2564 enum n_ia32_xDiv { 2565 n_ia32_xDiv_base = 0, 2566 n_ia32_xDiv_index = 1, 2567 n_ia32_xDiv_mem = 2, 2568 n_ia32_xDiv_dividend = 3, 2569 n_ia32_xDiv_divisor = 4, 2570 }; 2571 2572 enum pn_ia32_Test8Bit { 2573 pn_ia32_Test8Bit_eflags = 0, 2574 pn_ia32_Test8Bit_unused = 1, 2575 pn_ia32_Test8Bit_M = 2, 2576 }; 2577 2578 enum n_ia32_Test8Bit { 2579 n_ia32_Test8Bit_base = 0, 2580 n_ia32_Test8Bit_index = 1, 2581 n_ia32_Test8Bit_mem = 2, 2582 n_ia32_Test8Bit_left = 3, 2583 n_ia32_Test8Bit_right = 4, 2584 }; 2585 2586 enum pn_ia32_Sub { 2587 pn_ia32_Sub_res = 0, 2588 pn_ia32_Sub_flags = 1, 2589 pn_ia32_Sub_M = 2, 2590 }; 2591 2592 enum n_ia32_Sub { 2593 n_ia32_Sub_base = 0, 2594 n_ia32_Sub_index = 1, 2595 n_ia32_Sub_mem = 2, 2596 n_ia32_Sub_minuend = 3, 2597 n_ia32_Sub_subtrahend = 4, 2598 }; 2599 2600 enum pn_ia32_PrefetchNTA { 2601 pn_ia32_PrefetchNTA_M = 0, 2602 }; 2603 2604 enum n_ia32_PrefetchNTA { 2605 n_ia32_PrefetchNTA_base = 0, 2606 n_ia32_PrefetchNTA_index = 1, 2607 n_ia32_PrefetchNTA_mem = 2, 2608 }; 2609 2610 enum pn_ia32_Shr { 2611 pn_ia32_Shr_res = 0, 2612 pn_ia32_Shr_flags = 1, 2613 }; 2614 2615 enum n_ia32_Shr { 2616 n_ia32_Shr_val = 0, 2617 n_ia32_Shr_count = 1, 2618 }; 2619 2620 enum n_ia32_fprem { 2621 n_ia32_fprem_left = 0, 2622 n_ia32_fprem_right = 1, 2623 n_ia32_fprem_fpcw = 2, 2624 }; 2625 2626 enum pn_ia32_IDiv { 2627 pn_ia32_IDiv_div_res = 0, 2628 pn_ia32_IDiv_flags = 1, 2629 pn_ia32_IDiv_M = 2, 2630 pn_ia32_IDiv_mod_res = 3, 2631 pn_ia32_IDiv_X_regular = 4, 2632 pn_ia32_IDiv_X_except = 5, 2633 }; 2634 2635 enum n_ia32_IDiv { 2636 n_ia32_IDiv_base = 0, 2637 n_ia32_IDiv_index = 1, 2638 n_ia32_IDiv_mem = 2, 2639 n_ia32_IDiv_divisor = 3, 2640 n_ia32_IDiv_dividend_low = 4, 2641 n_ia32_IDiv_dividend_high = 5, 2642 }; 2643 2644 enum n_ia32_l_Adc { 2645 n_ia32_l_Adc_left = 0, 2646 n_ia32_l_Adc_right = 1, 2647 n_ia32_l_Adc_eflags = 2, 2648 }; 2649 2650 enum pn_ia32_Setcc { 2651 pn_ia32_Setcc_res = 0, 2652 }; 2653 2654 enum n_ia32_Setcc { 2655 n_ia32_Setcc_eflags = 0, 2656 }; 2657 2658 enum n_ia32_l_LLtoFloat { 2659 n_ia32_l_LLtoFloat_val_high = 0, 2660 n_ia32_l_LLtoFloat_val_low = 1, 2661 }; 2662 2663 enum pn_ia32_Bswap { 2664 pn_ia32_Bswap_res = 0, 2665 }; 2666 2667 enum n_ia32_Bswap { 2668 n_ia32_Bswap_val = 0, 2669 }; 2670 2671 enum n_ia32_SetccMem { 2672 n_ia32_SetccMem_base = 0, 2673 n_ia32_SetccMem_index = 1, 2674 n_ia32_SetccMem_mem = 2, 2675 n_ia32_SetccMem_eflags = 3, 2676 }; 2677 2678 enum pn_ia32_Test { 2679 pn_ia32_Test_eflags = 0, 2680 pn_ia32_Test_unused = 1, 2681 pn_ia32_Test_M = 2, 2682 }; 2683 2684 enum n_ia32_Test { 2685 n_ia32_Test_base = 0, 2686 n_ia32_Test_index = 1, 2687 n_ia32_Test_mem = 2, 2688 n_ia32_Test_left = 3, 2689 n_ia32_Test_right = 4, 2690 }; 2691 2692 enum n_ia32_l_Add { 2693 n_ia32_l_Add_left = 0, 2694 n_ia32_l_Add_right = 1, 2695 }; 2696 2697 enum pn_ia32_AddSP { 2698 pn_ia32_AddSP_stack = 0, 2699 pn_ia32_AddSP_M = 1, 2700 }; 2701 2702 enum n_ia32_AddSP { 2703 n_ia32_AddSP_base = 0, 2704 n_ia32_AddSP_index = 1, 2705 n_ia32_AddSP_mem = 2, 2706 n_ia32_AddSP_stack = 3, 2707 n_ia32_AddSP_size = 4, 2708 }; 2709 2710 enum n_ia32_RolMem { 2711 n_ia32_RolMem_base = 0, 2712 n_ia32_RolMem_index = 1, 2713 n_ia32_RolMem_mem = 2, 2714 n_ia32_RolMem_count = 3, 2715 }; 2716 2717 enum n_ia32_Conv_I2FP { 2718 n_ia32_Conv_I2FP_base = 0, 2719 n_ia32_Conv_I2FP_index = 1, 2720 n_ia32_Conv_I2FP_mem = 2, 2721 n_ia32_Conv_I2FP_val = 3, 2722 }; 2723 2724 enum n_ia32_Conv_FP2FP { 2725 n_ia32_Conv_FP2FP_base = 0, 2726 n_ia32_Conv_FP2FP_index = 1, 2727 n_ia32_Conv_FP2FP_mem = 2, 2728 n_ia32_Conv_FP2FP_val = 3, 2729 }; 2730 2731 enum pn_ia32_Prefetch2 { 2732 pn_ia32_Prefetch2_M = 0, 2733 }; 2734 2735 enum n_ia32_Prefetch2 { 2736 n_ia32_Prefetch2_base = 0, 2737 n_ia32_Prefetch2_index = 1, 2738 n_ia32_Prefetch2_mem = 2, 2739 }; 2740 2741 enum pn_ia32_Minus64Bit { 2742 pn_ia32_Minus64Bit_low_res = 0, 2743 pn_ia32_Minus64Bit_high_res = 1, 2744 }; 2745 2746 enum n_ia32_FnstCW { 2747 n_ia32_FnstCW_base = 0, 2748 n_ia32_FnstCW_index = 1, 2749 n_ia32_FnstCW_mem = 2, 2750 n_ia32_FnstCW_fpcw = 3, 2751 }; 2752 2753 enum pn_ia32_Prefetch0 { 2754 pn_ia32_Prefetch0_M = 0, 2755 }; 2756 2757 enum n_ia32_Prefetch0 { 2758 n_ia32_Prefetch0_base = 0, 2759 n_ia32_Prefetch0_index = 1, 2760 n_ia32_Prefetch0_mem = 2, 2761 }; 2762 2763 enum n_ia32_OrMem { 2764 n_ia32_OrMem_base = 0, 2765 n_ia32_OrMem_index = 1, 2766 n_ia32_OrMem_mem = 2, 2767 n_ia32_OrMem_val = 3, 2768 }; 2769 2770 enum pn_ia32_fldlg2 { 2771 pn_ia32_fldlg2_res = 0, 2772 }; 2773 2774 enum pn_ia32_fld1 { 2775 pn_ia32_fld1_res = 0, 2776 }; 2777 2778 enum n_ia32_Conv_FP2I { 2779 n_ia32_Conv_FP2I_base = 0, 2780 n_ia32_Conv_FP2I_index = 1, 2781 n_ia32_Conv_FP2I_mem = 2, 2782 n_ia32_Conv_FP2I_val = 3, 2783 }; 2784 2785 enum pn_ia32_Popcnt { 2786 pn_ia32_Popcnt_res = 0, 2787 pn_ia32_Popcnt_flags = 1, 2788 pn_ia32_Popcnt_M = 2, 2789 }; 2790 2791 enum n_ia32_Popcnt { 2792 n_ia32_Popcnt_base = 0, 2793 n_ia32_Popcnt_index = 1, 2794 n_ia32_Popcnt_mem = 2, 2795 n_ia32_Popcnt_operand = 3, 2796 }; 2797 2798 enum pn_ia32_Ror { 2799 pn_ia32_Ror_res = 0, 2800 pn_ia32_Ror_flags = 1, 2801 }; 2802 2803 enum n_ia32_Ror { 2804 n_ia32_Ror_val = 0, 2805 n_ia32_Ror_count = 1, 2806 }; 2807 2808 enum pn_ia32_Shl { 2809 pn_ia32_Shl_res = 0, 2810 pn_ia32_Shl_flags = 1, 2811 }; 2812 2813 enum n_ia32_Shl { 2814 n_ia32_Shl_val = 0, 2815 n_ia32_Shl_count = 1, 2816 }; 2817 2818 enum n_ia32_AndMem8Bit { 2819 n_ia32_AndMem8Bit_base = 0, 2820 n_ia32_AndMem8Bit_index = 1, 2821 n_ia32_AndMem8Bit_mem = 2, 2822 n_ia32_AndMem8Bit_val = 3, 2823 }; 2824 2825 enum pn_ia32_Add { 2826 pn_ia32_Add_res = 0, 2827 pn_ia32_Add_flags = 1, 2828 pn_ia32_Add_M = 2, 2829 }; 2830 2831 enum n_ia32_Add { 2832 n_ia32_Add_base = 0, 2833 n_ia32_Add_index = 1, 2834 n_ia32_Add_mem = 2, 2835 n_ia32_Add_left = 3, 2836 n_ia32_Add_right = 4, 2837 }; 2838 2839 enum pn_ia32_SubSP { 2840 pn_ia32_SubSP_stack = 0, 2841 pn_ia32_SubSP_addr = 1, 2842 pn_ia32_SubSP_M = 2, 2843 }; 2844 2845 enum n_ia32_SubSP { 2846 n_ia32_SubSP_base = 0, 2847 n_ia32_SubSP_index = 1, 2848 n_ia32_SubSP_mem = 2, 2849 n_ia32_SubSP_stack = 3, 2850 n_ia32_SubSP_size = 4, 2851 }; 2852 2853 enum pn_ia32_PrefetchW { 2854 pn_ia32_PrefetchW_M = 0, 2855 }; 2856 2857 enum n_ia32_PrefetchW { 2858 n_ia32_PrefetchW_base = 0, 2859 n_ia32_PrefetchW_index = 1, 2860 n_ia32_PrefetchW_mem = 2, 2861 }; 2862 2863 enum pn_ia32_Conv_I2I { 2864 pn_ia32_Conv_I2I_res = 0, 2865 pn_ia32_Conv_I2I_flags = 1, 2866 pn_ia32_Conv_I2I_M = 2, 2867 pn_ia32_Conv_I2I_X_regular = 3, 2868 pn_ia32_Conv_I2I_X_except = 4, 2869 }; 2870 2871 enum n_ia32_Conv_I2I { 2872 n_ia32_Conv_I2I_base = 0, 2873 n_ia32_Conv_I2I_index = 1, 2874 n_ia32_Conv_I2I_mem = 2, 2875 n_ia32_Conv_I2I_val = 3, 2876 }; 2877 2878 enum n_ia32_fchs { 2879 n_ia32_fchs_value = 0, 2880 }; 2881 2882 enum pn_ia32_ShrD { 2883 pn_ia32_ShrD_res = 0, 2884 pn_ia32_ShrD_flags = 1, 2885 }; 2886 2887 enum n_ia32_ShrD { 2888 n_ia32_ShrD_val_high = 0, 2889 n_ia32_ShrD_val_low = 1, 2890 n_ia32_ShrD_count = 2, 2891 }; 2892 2893 enum n_ia32_UD2 { 2894 n_ia32_UD2_mem = 0, 2895 }; 2896 2897 enum pn_ia32_Cwtl { 2898 pn_ia32_Cwtl_res = 0, 2899 }; 2900 2901 enum n_ia32_Cwtl { 2902 n_ia32_Cwtl_val = 0, 2903 }; 2904 2905 enum n_ia32_fabs { 2906 n_ia32_fabs_value = 0, 2907 }; 2908 2909 enum pn_ia32_fldpi { 2910 pn_ia32_fldpi_res = 0, 2911 }; 2912 2913 enum pn_ia32_Leave { 2914 pn_ia32_Leave_frame = 0, 2915 pn_ia32_Leave_stack = 1, 2916 }; 2917 2918 enum pn_ia32_Neg { 2919 pn_ia32_Neg_res = 0, 2920 pn_ia32_Neg_flags = 1, 2921 }; 2922 2923 enum n_ia32_Neg { 2924 n_ia32_Neg_val = 0, 2925 }; 2926 2927 enum pn_ia32_IMul1OP { 2928 pn_ia32_IMul1OP_res_low = 0, 2929 pn_ia32_IMul1OP_flags = 1, 2930 pn_ia32_IMul1OP_M = 2, 2931 pn_ia32_IMul1OP_res_high = 3, 2932 }; 2933 2934 enum n_ia32_IMul1OP { 2935 n_ia32_IMul1OP_base = 0, 2936 n_ia32_IMul1OP_index = 1, 2937 n_ia32_IMul1OP_mem = 2, 2938 n_ia32_IMul1OP_left = 3, 2939 n_ia32_IMul1OP_right = 4, 2940 }; 2941 2942 enum pn_ia32_PopMem { 2943 pn_ia32_PopMem_unused0 = 0, 2944 pn_ia32_PopMem_M = 1, 2945 pn_ia32_PopMem_unused1 = 2, 2946 pn_ia32_PopMem_stack = 3, 2947 }; 2948 2949 enum n_ia32_PopMem { 2950 n_ia32_PopMem_base = 0, 2951 n_ia32_PopMem_index = 1, 2952 n_ia32_PopMem_mem = 2, 2953 n_ia32_PopMem_stack = 3, 2954 }; 2955 2956 enum pn_ia32_fld { 2957 pn_ia32_fld_res = 0, 2958 pn_ia32_fld_unused = 1, 2959 pn_ia32_fld_M = 2, 2960 pn_ia32_fld_X_regular = 3, 2961 pn_ia32_fld_X_except = 4, 2962 }; 2963 2964 enum n_ia32_fld { 2965 n_ia32_fld_base = 0, 2966 n_ia32_fld_index = 1, 2967 n_ia32_fld_mem = 2, 2968 }; 2969 2970 enum pn_ia32_Dec { 2971 pn_ia32_Dec_res = 0, 2972 pn_ia32_Dec_flags = 1, 2973 }; 2974 2975 enum n_ia32_Dec { 2976 n_ia32_Dec_val = 0, 2977 }; 2978 2979 enum pn_ia32_Pop { 2980 pn_ia32_Pop_res = 0, 2981 pn_ia32_Pop_M = 1, 2982 pn_ia32_Pop_unused = 2, 2983 pn_ia32_Pop_stack = 3, 2984 }; 2985 2986 enum n_ia32_Pop { 2987 n_ia32_Pop_mem = 0, 2988 n_ia32_Pop_stack = 1, 2989 }; 2990 2991 enum pn_ia32_CopyEbpEsp { 2992 pn_ia32_CopyEbpEsp_esp = 0, 2993 }; 2994 2995 enum n_ia32_CopyEbpEsp { 2996 n_ia32_CopyEbpEsp_ebp = 0, 2997 }; 2998 2999 enum pn_ia32_Not { 3000 pn_ia32_Not_res = 0, 3001 }; 3002 3003 enum n_ia32_Not { 3004 n_ia32_Not_val = 0, 3005 }; 3006 3007 enum n_ia32_AndMem { 3008 n_ia32_AndMem_base = 0, 3009 n_ia32_AndMem_index = 1, 3010 n_ia32_AndMem_mem = 2, 3011 n_ia32_AndMem_val = 3, 3012 }; 3013 3014 enum pn_ia32_xStoreSimple { 3015 pn_ia32_xStoreSimple_M = 0, 3016 pn_ia32_xStoreSimple_X_regular = 1, 3017 pn_ia32_xStoreSimple_X_except = 2, 3018 }; 3019 3020 enum n_ia32_xStoreSimple { 3021 n_ia32_xStoreSimple_base = 0, 3022 n_ia32_xStoreSimple_index = 1, 3023 n_ia32_xStoreSimple_mem = 2, 3024 n_ia32_xStoreSimple_val = 3, 3025 }; 3026 3027 enum pn_ia32_And { 3028 pn_ia32_And_res = 0, 3029 pn_ia32_And_flags = 1, 3030 pn_ia32_And_M = 2, 3031 }; 3032 3033 enum n_ia32_And { 3034 n_ia32_And_base = 0, 3035 n_ia32_And_index = 1, 3036 n_ia32_And_mem = 2, 3037 n_ia32_And_left = 3, 3038 n_ia32_And_right = 4, 3039 }; 3040 3041 enum pn_ia32_Jcc { 3042 pn_ia32_Jcc_false = 0, 3043 pn_ia32_Jcc_true = 1, 3044 }; 3045 3046 enum n_ia32_Jcc { 3047 n_ia32_Jcc_eflags = 0, 3048 }; 3049 3050 enum n_ia32_l_Sbb { 3051 n_ia32_l_Sbb_minuend = 0, 3052 n_ia32_l_Sbb_subtrahend = 1, 3053 n_ia32_l_Sbb_eflags = 2, 3054 }; 3055 3056 enum pn_ia32_Bsr { 3057 pn_ia32_Bsr_res = 0, 3058 pn_ia32_Bsr_flags = 1, 3059 pn_ia32_Bsr_M = 2, 3060 }; 3061 3062 enum n_ia32_Bsr { 3063 n_ia32_Bsr_base = 0, 3064 n_ia32_Bsr_index = 1, 3065 n_ia32_Bsr_mem = 2, 3066 n_ia32_Bsr_operand = 3, 3067 }; 3068 3069 enum n_ia32_Bswap16 { 3070 n_ia32_Bswap16_val = 0, 3071 }; 3072 3073 enum pn_ia32_Inport { 3074 pn_ia32_Inport_res = 0, 3075 pn_ia32_Inport_M = 1, 3076 }; 3077 3078 enum n_ia32_Inport { 3079 n_ia32_Inport_port = 0, 3080 n_ia32_Inport_mem = 1, 3081 }; 3082 3083 enum n_ia32_SarMem { 3084 n_ia32_SarMem_base = 0, 3085 n_ia32_SarMem_index = 1, 3086 n_ia32_SarMem_mem = 2, 3087 n_ia32_SarMem_count = 3, 3088 }; 3089 3090 enum pn_ia32_Adc { 3091 pn_ia32_Adc_res = 0, 3092 pn_ia32_Adc_flags = 1, 3093 pn_ia32_Adc_M = 2, 3094 }; 3095 3096 enum n_ia32_Adc { 3097 n_ia32_Adc_base = 0, 3098 n_ia32_Adc_index = 1, 3099 n_ia32_Adc_mem = 2, 3100 n_ia32_Adc_left = 3, 3101 n_ia32_Adc_right = 4, 3102 n_ia32_Adc_eflags = 5, 3103 }; 3104 3105 enum pn_ia32_l_Mul { 3106 pn_ia32_l_Mul_res_low = 0, 3107 pn_ia32_l_Mul_flags = 1, 3108 pn_ia32_l_Mul_M = 2, 3109 pn_ia32_l_Mul_res_high = 3, 3110 }; 3111 3112 enum n_ia32_l_Mul { 3113 n_ia32_l_Mul_left = 0, 3114 n_ia32_l_Mul_right = 1, 3115 }; 3116 3117 enum pn_ia32_xAndNot { 3118 pn_ia32_xAndNot_res = 0, 3119 pn_ia32_xAndNot_flags = 1, 3120 pn_ia32_xAndNot_M = 2, 3121 }; 3122 3123 enum n_ia32_xAndNot { 3124 n_ia32_xAndNot_base = 0, 3125 n_ia32_xAndNot_index = 1, 3126 n_ia32_xAndNot_mem = 2, 3127 n_ia32_xAndNot_left = 3, 3128 n_ia32_xAndNot_right = 4, 3129 }; 3130 3131 enum pn_ia32_Load { 3132 pn_ia32_Load_res = 0, 3133 pn_ia32_Load_unused = 1, 3134 pn_ia32_Load_M = 2, 3135 pn_ia32_Load_X_regular = 3, 3136 pn_ia32_Load_X_except = 4, 3137 }; 3138 3139 enum n_ia32_Load { 3140 n_ia32_Load_base = 0, 3141 n_ia32_Load_index = 1, 3142 n_ia32_Load_mem = 2, 3143 }; 3144 3145 enum pn_ia32_Prefetch { 3146 pn_ia32_Prefetch_M = 0, 3147 }; 3148 3149 enum n_ia32_Prefetch { 3150 n_ia32_Prefetch_base = 0, 3151 n_ia32_Prefetch_index = 1, 3152 n_ia32_Prefetch_mem = 2, 3153 }; 3154 3155 3156 #endif 3157