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Searched refs:port_iter (Results 1 – 25 of 32) sorted by relevance

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/dports/cad/openroad/OpenROAD-2.0/src/sta/verilog/
H A DVerilogWriter.cc140 CellPortIterator *port_iter = network_->portIterator(cell); in writePorts() local
141 while (port_iter->hasNext()) { in writePorts()
142 Port *port = port_iter->next(); in writePorts()
152 delete port_iter; in writePorts()
159 CellPortIterator *port_iter = network_->portIterator(cell); in writePortDcls() local
160 while (port_iter->hasNext()) { in writePortDcls()
161 Port *port = port_iter->next(); in writePortDcls()
186 delete port_iter; in writePortDcls()
284 while (port_iter->hasNext()) { in writeChild()
285 Port *port = port_iter->next(); in writeChild()
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H A DVerilogReader.cc1717 while (port_iter.hasNext()) { in linkNetwork()
1718 VerilogNet *mod_port = port_iter.next(); in linkNetwork()
1826 while (port_iter.hasNext()) { in makeModuleInstNetwork()
1827 LibertyPort *port = port_iter.next(); in makeModuleInstNetwork()
1877 while (port_iter->hasNext()) { in makeNamedInstPins()
1878 Port *port = port_iter->next(); in makeNamedInstPins()
1882 delete port_iter; in makeNamedInstPins()
1920 Port *port = port_iter->next(); in makeOrderedInstPins()
1946 delete port_iter; in makeOrderedInstPins()
2004 while (port_iter.hasNext()) { in makeLibertyInst()
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/dports/cad/openroad/OpenROAD-2.0/src/sta/liberty/
H A DEquivCells.cc56 LibertyCellPortBitIterator port_iter(cell); in cellDriveResistance() local
57 while (port_iter.hasNext()) { in cellDriveResistance()
58 auto port = port_iter.next(); in cellDriveResistance()
184 LibertyCellPortIterator port_iter(cell); in hashCellPorts() local
185 while (port_iter.hasNext()) { in hashCellPorts()
186 LibertyPort *port = port_iter.next(); in hashCellPorts()
205 LibertyCellPgPortIterator port_iter(cell); in hashCellPgPorts() local
206 while (port_iter.hasNext()) { in hashCellPgPorts()
207 LibertyPgPort *port = port_iter.next(); in hashCellPgPorts()
H A DLibertyReader.cc1852 while (port_iter.hasNext()) { in finishPortGroups()
1888 while (port_iter.hasNext()) { in makeTimingArcs()
1903 while (port_iter.hasNext()) { in makeInternalPowers()
2540 while (port_iter.hasNext()) { in beginPin()
2619 while (port_iter.hasNext()) { in endPorts()
2823 while (port_iter.hasNext()) { in visitDirection()
2841 while (port_iter.hasNext()) { in visitFunction()
2869 while (port_iter.hasNext()) { in visitPorts()
3191 while (port_iter.hasNext()) { in visitPulseClock()
4539 while (port_iter.hasNext()) { in visitRelatedGroundPin()
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H A DLibertyBuilder.cc368 FuncExprPortIterator port_iter(to_func); in makeRegLatchArcs() local
369 while (port_iter.hasNext()) { in makeRegLatchArcs()
370 LibertyPort *func_port = port_iter.next(); in makeRegLatchArcs()
H A DLiberty.cc915 LibertyCellPortIterator port_iter(this); in findLibertyPortsMatching() local
916 while (port_iter.hasNext()) { in findLibertyPortsMatching()
917 LibertyPort *port = port_iter.next(); in findLibertyPortsMatching()
2401 LibertyPortSet::Iterator port_iter(set); in sortLibertyPortSet() local
2402 while (port_iter.hasNext()) in sortLibertyPortSet()
2403 ports.push_back(port_iter.next()); in sortLibertyPortSet()
/dports/cad/openroad/OpenROAD-2.0/src/sta/network/
H A DNetworkCmp.cc93 PortSet::Iterator port_iter(set); in sortPortSet() local
94 while (port_iter.hasNext()) in sortPortSet()
95 ports.push_back(port_iter.next()); in sortPortSet()
H A DConcreteLibrary.cc281 ConcreteCellPortIterator *port_iter = portIterator(); in findPortsMatching() local
282 while (port_iter->hasNext()) { in findPortsMatching()
283 ConcretePort *port = port_iter->next(); in findPortsMatching()
296 delete port_iter; in findPortsMatching()
H A DSdcNetwork.cc872 CellPortIterator *port_iter = network_->portIterator(cell); in visitPinTail() local
873 while (port_iter->hasNext()) { in visitPinTail()
874 Port *port = port_iter->next(); in visitPinTail()
909 delete port_iter; in visitPinTail()
/dports/cad/openroad/OpenROAD-2.0/src/sta/sdc/
H A DWriteSdc.cc1103 while (port_iter.hasNext()) { in writeDisabledPorts()
1117 while (port_iter.hasNext()) { in writeDisabledLibPorts()
1657 while (port_iter->hasNext()) { in writePortLoads()
1661 delete port_iter; in writePortLoads()
1685 while (port_iter->hasNext()) { in writeDriveResistances()
1720 delete port_iter; in writeDriveResistances()
1776 delete port_iter; in writeDrivingCells()
1826 delete port_iter; in writeInputTransitions()
2287 delete port_iter; in writeSlewLimits()
2375 while (port_iter.hasNext()) { in writeCapLimits()
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H A DSdcGraph.cc83 PortSet::Iterator port_iter(disabled_ports_); in annotateDisables() local
84 while (port_iter.hasNext()) { in annotateDisables()
85 Port *port = port_iter.next(); in annotateDisables()
/dports/cad/openroad/OpenROAD-2.0/src/dbSta/src/
H A DdbSdcNetwork.cc184 CellPortIterator *port_iter = network_->portIterator(cell); in findMatchingPins() local
185 while (port_iter->hasNext()) { in findMatchingPins()
186 Port *port = port_iter->next(); in findMatchingPins()
215 delete port_iter; in findMatchingPins()
H A DdbNetwork.cc984 ConcreteCellPortBitIterator *port_iter = ccell->portBitIterator(); in readLibertyAfter() local
985 while (port_iter->hasNext()) { in readLibertyAfter()
986 ConcretePort *cport = port_iter->next(); in readLibertyAfter()
999 delete port_iter; in readLibertyAfter()
/dports/net/zerotier/ZeroTierOne-1.8.3/ext/redis-plus-plus-1.1.1/src/sw/redis++/
H A Dsentinel.cpp258 auto port_iter = slave.find("port"); in _parse_slave_info() local
259 if (flags_iter == slave.end() || ip_iter == slave.end() || port_iter == slave.end()) { in _parse_slave_info()
270 port = std::stoi(port_iter->second); in _parse_slave_info()
272 throw ProtoError("Slave port is invalid: " + port_iter->second); in _parse_slave_info()
/dports/audio/qjackctl/qjackctl-qjackctl_0_9_5/src/
H A DqjackctlAliases.cpp272 QStringListIterator port_iter(settings.childGroups()); in loadSettings() local
273 while (port_iter.hasNext()) { in loadSettings()
275 = port_iter.next(); in loadSettings()
H A DqjackctlPatchbayRack.cpp131 QStringListIterator port_iter(ports);
134 && plug_iter.hasNext() && port_iter.hasNext()) {
136 const QString& sPort = port_iter.next();
153 QStringListIterator port_iter(ports);
154 while (port_iter.hasNext()) {
156 qjackctlAliasItem::escapeRegExpDigits(port_iter.next()));
/dports/cad/openroad/OpenROAD-2.0/src/sta/search/
H A DWriteSpice.cc395 StringVector::Iterator port_iter(spice_port_names); in writeGateStage() local
396 while (port_iter.hasNext()) { in writeGateStage()
397 const char *subckt_port_name = port_iter.next().c_str(); in writeGateStage()
490 StringVector::Iterator port_iter(spice_port_names); in writeStageVoltageSources() local
491 while (port_iter.hasNext()) { in writeStageVoltageSources()
492 auto subckt_port_name = port_iter.next().c_str(); in writeStageVoltageSources()
H A DFindRegister.cc437 FuncExprPortIterator port_iter(expr); in visitExpr() local
438 while (port_iter.hasNext()) { in visitExpr()
439 LibertyPort *port = port_iter.next(); in visitExpr()
H A DPower.cc921 FuncExprPortIterator port_iter(when); in findLeakagePower() local
923 while (port_iter.hasNext()) { in findLeakagePower()
924 LibertyPort *port = port_iter.next(); in findLeakagePower()
H A DSim.cc986 LibertyCellPortIterator port_iter(cell); in clockGateOutValue() local
987 while (port_iter.hasNext()) { in clockGateOutValue()
988 LibertyPort *port = port_iter.next(); in clockGateOutValue()
/dports/biology/ncbi-cxx-toolkit/ncbi_cxx--25_2_0/src/connect/
H A Dncbi_monkey.cpp1130 auto port_iter = m_PortRanges.begin(); in Match() local
1131 for (; port_iter != m_PortRanges.end(); port_iter++) { in Match()
1132 if (sock_port >= *port_iter && sock_port <= *++port_iter) { in Match()
/dports/biology/ncbi-blast+/ncbi-blast-2.12.0+-src/c++/src/connect/
H A Dncbi_monkey.cpp1130 auto port_iter = m_PortRanges.begin(); in Match() local
1131 for (; port_iter != m_PortRanges.end(); port_iter++) { in Match()
1132 if (sock_port >= *port_iter && sock_port <= *++port_iter) { in Match()
/dports/cad/openroad/OpenROAD-2.0/src/sta/tcl/
H A DStaTcl.i502 while (port_iter.hasNext()) {
503 Port *port = port_iter.next();
515 while (port_iter.hasNext()) {
2318 while (port_iter.hasNext()) { in find_ports_matching()
2319 Port *port = port_iter.next(); in find_ports_matching()
2347 PortSeq::Iterator port_iter(ports); in find_port_pins_matching()
2348 while (port_iter.hasNext()) { in find_port_pins_matching()
2349 Port *port = port_iter.next(); in find_port_pins_matching()
2556 PortSeq::Iterator port_iter(ports); in filter_ports()
2558 while (port_iter.hasNext()) { in filter_ports()
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H A DSdc.tcl2379 set port_iter [$cell liberty_port_iterator]
2381 while {[$port_iter has_next]} {
2382 set port [$port_iter next]
2387 $port_iter finish
2395 $port_iter finish
/dports/cad/openroad/OpenROAD-2.0/src/rsz/src/
H A DResizer.cc454 InstancePinIterator *port_iter = network_->pinIterator(network_->topInstance()); in bufferInputs() local
455 while (port_iter->hasNext()) { in bufferInputs()
456 Pin *pin = port_iter->next(); in bufferInputs()
466 delete port_iter; in bufferInputs()
549 InstancePinIterator *port_iter = network_->pinIterator(network_->topInstance()); in bufferOutputs() local
550 while (port_iter->hasNext()) { in bufferOutputs()
551 Pin *pin = port_iter->next(); in bufferOutputs()
560 delete port_iter; in bufferOutputs()

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