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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
19 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
28 ; CHECK-NEXT: stxvp vsp34, 128(r1) # 32-byte Folded Spill
30 ; CHECK-NEXT: stxvp vsp36, 96(r1) # 32-byte Folded Spill
42 ; CHECK-NEXT: lxvp vsp36, 96(r1) # 32-byte Folded Reload
52 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dspill-vec-pair.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; CHECK-NEXT: stfd f14, 256(r1) # 8-byte Folded Spill
13 ; CHECK-NEXT: stfd f15, 264(r1) # 8-byte Folded Spill
14 ; CHECK-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
15 ; CHECK-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
16 ; CHECK-NEXT: stfd f16, 272(r1) # 8-byte Folded Spill
156 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
159 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
163 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
19 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
28 ; CHECK-NEXT: stxvp vsp34, 128(r1) # 32-byte Folded Spill
30 ; CHECK-NEXT: stxvp vsp36, 96(r1) # 32-byte Folded Spill
42 ; CHECK-NEXT: lxvp vsp36, 96(r1) # 32-byte Folded Reload
52 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dspill-vec-pair.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; CHECK-NEXT: stfd f14, 256(r1) # 8-byte Folded Spill
13 ; CHECK-NEXT: stfd f15, 264(r1) # 8-byte Folded Spill
14 ; CHECK-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
15 ; CHECK-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
16 ; CHECK-NEXT: stfd f16, 272(r1) # 8-byte Folded Spill
156 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
159 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
163 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
19 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
28 ; CHECK-NEXT: stxvp vsp34, 128(r1) # 32-byte Folded Spill
30 ; CHECK-NEXT: stxvp vsp36, 96(r1) # 32-byte Folded Spill
42 ; CHECK-NEXT: lxvp vsp36, 96(r1) # 32-byte Folded Reload
52 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dspill-vec-pair.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; CHECK-NEXT: stfd f14, 256(r1) # 8-byte Folded Spill
13 ; CHECK-NEXT: stfd f15, 264(r1) # 8-byte Folded Spill
14 ; CHECK-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
15 ; CHECK-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
16 ; CHECK-NEXT: stfd f16, 272(r1) # 8-byte Folded Spill
156 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
159 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
163 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
19 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
28 ; CHECK-NEXT: stxvp vsp34, 128(r1) # 32-byte Folded Spill
30 ; CHECK-NEXT: stxvp vsp36, 96(r1) # 32-byte Folded Spill
42 ; CHECK-NEXT: lxvp vsp36, 96(r1) # 32-byte Folded Reload
52 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dspill-vec-pair.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; CHECK-NEXT: stfd f14, 256(r1) # 8-byte Folded Spill
13 ; CHECK-NEXT: stfd f15, 264(r1) # 8-byte Folded Spill
14 ; CHECK-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
15 ; CHECK-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
16 ; CHECK-NEXT: stfd f16, 272(r1) # 8-byte Folded Spill
156 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
159 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
163 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
19 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
28 ; CHECK-NEXT: stxvp vsp34, 128(r1) # 32-byte Folded Spill
30 ; CHECK-NEXT: stxvp vsp36, 96(r1) # 32-byte Folded Spill
42 ; CHECK-NEXT: lxvp vsp36, 96(r1) # 32-byte Folded Reload
52 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dspill-vec-pair.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; CHECK-NEXT: stfd f14, 256(r1) # 8-byte Folded Spill
13 ; CHECK-NEXT: stfd f15, 264(r1) # 8-byte Folded Spill
14 ; CHECK-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
15 ; CHECK-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
16 ; CHECK-NEXT: stfd f16, 272(r1) # 8-byte Folded Spill
156 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
159 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
163 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
20 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
31 ; CHECK-NEXT: stxvp vsp34, r1(r3) # 32-byte Folded Spill
35 ; CHECK-NEXT: stxvp vsp36, r1(r3) # 32-byte Folded Spill
49 ; CHECK-NEXT: lxvp vsp34, r1(r3) # 32-byte Folded Reload
61 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmore-dq-form-prepare.ll481 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
483 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
485 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
530 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
532 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
534 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
536 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
538 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
540 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
542 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dmma-acc-spill.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
20 ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
31 ; CHECK-NEXT: stxvp vsp34, r1(r3) # 32-byte Folded Spill
35 ; CHECK-NEXT: stxvp vsp36, r1(r3) # 32-byte Folded Spill
49 ; CHECK-NEXT: lxvp vsp34, r1(r3) # 32-byte Folded Reload
61 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dvec-itofp.ll2 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
68 ; CHECK-P9-NEXT: .byte 9
69 ; CHECK-P9-NEXT: .byte 8
72 ; CHECK-P9-NEXT: .byte 5
73 ; CHECK-P9-NEXT: .byte 4
74 ; CHECK-P9-NEXT: .byte 3
75 ; CHECK-P9-NEXT: .byte 2
76 ; CHECK-P9-NEXT: .byte 1
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dvec-itofp.ll2 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
68 ; CHECK-P9-NEXT: .byte 9
69 ; CHECK-P9-NEXT: .byte 8
72 ; CHECK-P9-NEXT: .byte 5
73 ; CHECK-P9-NEXT: .byte 4
74 ; CHECK-P9-NEXT: .byte 3
75 ; CHECK-P9-NEXT: .byte 2
76 ; CHECK-P9-NEXT: .byte 1
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dvec-itofp.ll2 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
68 ; CHECK-P9-NEXT: .byte 9
69 ; CHECK-P9-NEXT: .byte 8
72 ; CHECK-P9-NEXT: .byte 5
73 ; CHECK-P9-NEXT: .byte 4
74 ; CHECK-P9-NEXT: .byte 3
75 ; CHECK-P9-NEXT: .byte 2
76 ; CHECK-P9-NEXT: .byte 1
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/
H A Dvec-itofp.ll2 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
68 ; CHECK-P9-NEXT: .byte 9
69 ; CHECK-P9-NEXT: .byte 8
72 ; CHECK-P9-NEXT: .byte 5
73 ; CHECK-P9-NEXT: .byte 4
74 ; CHECK-P9-NEXT: .byte 3
75 ; CHECK-P9-NEXT: .byte 2
76 ; CHECK-P9-NEXT: .byte 1
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dvec-itofp.ll2 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
68 ; CHECK-P9-NEXT: .byte 9
69 ; CHECK-P9-NEXT: .byte 8
72 ; CHECK-P9-NEXT: .byte 5
73 ; CHECK-P9-NEXT: .byte 4
74 ; CHECK-P9-NEXT: .byte 3
75 ; CHECK-P9-NEXT: .byte 2
76 ; CHECK-P9-NEXT: .byte 1
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/
H A Dvec-itofp.ll2 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
68 ; CHECK-P9-NEXT: .byte 9
69 ; CHECK-P9-NEXT: .byte 8
72 ; CHECK-P9-NEXT: .byte 5
73 ; CHECK-P9-NEXT: .byte 4
74 ; CHECK-P9-NEXT: .byte 3
75 ; CHECK-P9-NEXT: .byte 2
76 ; CHECK-P9-NEXT: .byte 1
[all …]

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