| /dports/devel/binutils/binutils-2.37/gas/testsuite/gas/tic6x/ |
| H A D | predicate-bad-2.l | 3 [^:]*:5: Error: instruction 'nop' cannot be predicated
4 [^:]*:6: Error: instruction 'nop' cannot be predicated
5 [^:]*:7: Error: instruction 'nop' cannot be predicated
6 [^:]*:8: Error: instruction 'nop' cannot be predicated
7 [^:]*:9: Error: instruction 'nop' cannot be predicated
8 [^:]*:10: Error: instruction 'nop' cannot be predicated
10 [^:]*:11: Error: instruction 'nop' cannot be predicated
11 [^:]*:12: Error: instruction 'nop' cannot be predicated
12 [^:]*:13: Error: instruction 'nop' cannot be predicated
13 [^:]*:14: Error: instruction 'nop' cannot be predicated
[all …]
|
| H A D | predicate-bad-3.l | 2 [^:]*:5: Error: instruction 'nop' cannot be predicated
3 [^:]*:6: Error: instruction 'nop' cannot be predicated
4 [^:]*:7: Error: instruction 'addab' cannot be predicated
5 [^:]*:8: Error: instruction 'addah' cannot be predicated
6 [^:]*:9: Error: instruction 'addaw' cannot be predicated
7 [^:]*:10: Error: instruction 'callp' cannot be predicated
8 [^:]*:11: Error: instruction 'addsub' cannot be predicated
9 [^:]*:12: Error: instruction 'addsub2' cannot be predicated
10 [^:]*:13: Error: instruction 'cmpy' cannot be predicated
11 [^:]*:14: Error: instruction 'cmpyr' cannot be predicated
[all …]
|
| /dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/tic6x/ |
| H A D | predicate-bad-2.l | 3 [^:]*:5: Error: instruction 'nop' cannot be predicated
4 [^:]*:6: Error: instruction 'nop' cannot be predicated
5 [^:]*:7: Error: instruction 'nop' cannot be predicated
6 [^:]*:8: Error: instruction 'nop' cannot be predicated
7 [^:]*:9: Error: instruction 'nop' cannot be predicated
8 [^:]*:10: Error: instruction 'nop' cannot be predicated
10 [^:]*:11: Error: instruction 'nop' cannot be predicated
11 [^:]*:12: Error: instruction 'nop' cannot be predicated
12 [^:]*:13: Error: instruction 'nop' cannot be predicated
13 [^:]*:14: Error: instruction 'nop' cannot be predicated
[all …]
|
| H A D | predicate-bad-3.l | 2 [^:]*:5: Error: instruction 'nop' cannot be predicated
3 [^:]*:6: Error: instruction 'nop' cannot be predicated
4 [^:]*:7: Error: instruction 'addab' cannot be predicated
5 [^:]*:8: Error: instruction 'addah' cannot be predicated
6 [^:]*:9: Error: instruction 'addaw' cannot be predicated
7 [^:]*:10: Error: instruction 'callp' cannot be predicated
8 [^:]*:11: Error: instruction 'addsub' cannot be predicated
9 [^:]*:12: Error: instruction 'addsub2' cannot be predicated
10 [^:]*:13: Error: instruction 'cmpy' cannot be predicated
11 [^:]*:14: Error: instruction 'cmpyr' cannot be predicated
[all …]
|
| /dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/tic6x/ |
| H A D | predicate-bad-2.l | 3 [^:]*:5: Error: instruction 'nop' cannot be predicated
4 [^:]*:6: Error: instruction 'nop' cannot be predicated
5 [^:]*:7: Error: instruction 'nop' cannot be predicated
6 [^:]*:8: Error: instruction 'nop' cannot be predicated
7 [^:]*:9: Error: instruction 'nop' cannot be predicated
8 [^:]*:10: Error: instruction 'nop' cannot be predicated
10 [^:]*:11: Error: instruction 'nop' cannot be predicated
11 [^:]*:12: Error: instruction 'nop' cannot be predicated
12 [^:]*:13: Error: instruction 'nop' cannot be predicated
13 [^:]*:14: Error: instruction 'nop' cannot be predicated
[all …]
|
| H A D | predicate-bad-3.l | 2 [^:]*:5: Error: instruction 'nop' cannot be predicated
3 [^:]*:6: Error: instruction 'nop' cannot be predicated
4 [^:]*:7: Error: instruction 'addab' cannot be predicated
5 [^:]*:8: Error: instruction 'addah' cannot be predicated
6 [^:]*:9: Error: instruction 'addaw' cannot be predicated
7 [^:]*:10: Error: instruction 'callp' cannot be predicated
8 [^:]*:11: Error: instruction 'addsub' cannot be predicated
9 [^:]*:12: Error: instruction 'addsub2' cannot be predicated
10 [^:]*:13: Error: instruction 'cmpy' cannot be predicated
11 [^:]*:14: Error: instruction 'cmpyr' cannot be predicated
[all …]
|
| /dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/tic6x/ |
| H A D | predicate-bad-2.l | 3 [^:]*:5: Error: instruction 'nop' cannot be predicated
4 [^:]*:6: Error: instruction 'nop' cannot be predicated
5 [^:]*:7: Error: instruction 'nop' cannot be predicated
6 [^:]*:8: Error: instruction 'nop' cannot be predicated
7 [^:]*:9: Error: instruction 'nop' cannot be predicated
8 [^:]*:10: Error: instruction 'nop' cannot be predicated
10 [^:]*:11: Error: instruction 'nop' cannot be predicated
11 [^:]*:12: Error: instruction 'nop' cannot be predicated
12 [^:]*:13: Error: instruction 'nop' cannot be predicated
13 [^:]*:14: Error: instruction 'nop' cannot be predicated
[all …]
|
| H A D | predicate-bad-3.l | 2 [^:]*:5: Error: instruction 'nop' cannot be predicated
3 [^:]*:6: Error: instruction 'nop' cannot be predicated
4 [^:]*:7: Error: instruction 'addab' cannot be predicated
5 [^:]*:8: Error: instruction 'addah' cannot be predicated
6 [^:]*:9: Error: instruction 'addaw' cannot be predicated
7 [^:]*:10: Error: instruction 'callp' cannot be predicated
8 [^:]*:11: Error: instruction 'addsub' cannot be predicated
9 [^:]*:12: Error: instruction 'addsub2' cannot be predicated
10 [^:]*:13: Error: instruction 'cmpy' cannot be predicated
11 [^:]*:14: Error: instruction 'cmpyr' cannot be predicated
[all …]
|
| /dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/tic6x/ |
| H A D | predicate-bad-2.l | 3 [^:]*:5: Error: instruction 'nop' cannot be predicated
4 [^:]*:6: Error: instruction 'nop' cannot be predicated
5 [^:]*:7: Error: instruction 'nop' cannot be predicated
6 [^:]*:8: Error: instruction 'nop' cannot be predicated
7 [^:]*:9: Error: instruction 'nop' cannot be predicated
8 [^:]*:10: Error: instruction 'nop' cannot be predicated
10 [^:]*:11: Error: instruction 'nop' cannot be predicated
11 [^:]*:12: Error: instruction 'nop' cannot be predicated
12 [^:]*:13: Error: instruction 'nop' cannot be predicated
13 [^:]*:14: Error: instruction 'nop' cannot be predicated
[all …]
|
| H A D | predicate-bad-3.l | 2 [^:]*:5: Error: instruction 'nop' cannot be predicated
3 [^:]*:6: Error: instruction 'nop' cannot be predicated
4 [^:]*:7: Error: instruction 'addab' cannot be predicated
5 [^:]*:8: Error: instruction 'addah' cannot be predicated
6 [^:]*:9: Error: instruction 'addaw' cannot be predicated
7 [^:]*:10: Error: instruction 'callp' cannot be predicated
8 [^:]*:11: Error: instruction 'addsub' cannot be predicated
9 [^:]*:12: Error: instruction 'addsub2' cannot be predicated
10 [^:]*:13: Error: instruction 'cmpy' cannot be predicated
11 [^:]*:14: Error: instruction 'cmpyr' cannot be predicated
[all …]
|
| /dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/arm/ |
| H A D | mve-vctp-bad.l | 12 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r0'
14 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r0'
16 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r0'
18 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r1'
20 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r1'
22 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r2'
24 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r2'
26 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r2'
28 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r4'
30 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r4'
[all …]
|
| /dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/arm/ |
| H A D | mve-vctp-bad.l | 12 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r0'
14 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r0'
16 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r0'
18 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r1'
20 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r1'
22 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r2'
24 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r2'
26 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r2'
28 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r4'
30 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r4'
[all …]
|
| /dports/devel/binutils/binutils-2.37/gas/testsuite/gas/arm/ |
| H A D | mve-vctp-bad.l | 12 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r0'
14 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r0'
16 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r0'
18 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r1'
20 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r1'
22 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r2'
24 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r2'
26 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r2'
28 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r4'
30 [^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r4'
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| H A D | mve-pred-constfold.ll | 21 %1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0)
23 %3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2)
24 %4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0)
25 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2)
54 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %1)
150 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
152 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
177 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
378 declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)
379 declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>)
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
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| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
|
| H A D | mve-pred-constfold.ll | 21 %1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0)
23 %3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2)
24 %4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0)
25 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2)
54 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %1)
150 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
152 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
177 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
378 declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)
379 declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>)
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-blocks.ll | 4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
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