| /dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 238 static void printAndVerify(PassManagerBase &PM, in printAndVerify() function
340 printAndVerify(PM, "After Instruction Selection"); in addCommonCodeGenPasses()
357 printAndVerify(PM, "After codegen DCE pass"); in addCommonCodeGenPasses()
371 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate"); in addCommonCodeGenPasses()
376 printAndVerify(PM, "After PreRegAlloc passes"); in addCommonCodeGenPasses()
380 printAndVerify(PM, "After Register Allocation"); in addCommonCodeGenPasses()
398 printAndVerify(PM, "After PostRegAlloc passes"); in addCommonCodeGenPasses()
401 printAndVerify(PM, "After LowerSubregs"); in addCommonCodeGenPasses()
405 printAndVerify(PM, "After PrologEpilogCodeInserter"); in addCommonCodeGenPasses()
409 printAndVerify(PM, "After PreSched2 passes"); in addCommonCodeGenPasses()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 350 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
358 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
364 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
383 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
389 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
395 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
398 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 351 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
359 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
365 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
384 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
390 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
396 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
399 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 350 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
358 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
364 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
383 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
389 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
395 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
398 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 351 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
359 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
365 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
384 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
390 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
396 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
399 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 350 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
358 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
364 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
383 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
389 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
395 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
398 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 351 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
359 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
365 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
384 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
390 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
396 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
399 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 350 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
358 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
364 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
383 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
389 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
395 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
398 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 345 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
353 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
359 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
378 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
384 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
390 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
393 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 342 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
350 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
356 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
375 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
381 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
387 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
390 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 382 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
390 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
396 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
415 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
421 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
427 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
430 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 382 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
390 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
396 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
415 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
421 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
427 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
430 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 378 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
386 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
392 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
411 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
417 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
423 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
426 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 382 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
390 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
396 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
415 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
421 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
427 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
430 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 382 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
390 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
396 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
415 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
421 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
427 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
430 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 382 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
390 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
396 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
415 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
421 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
427 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
430 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 378 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
386 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
392 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
411 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
417 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
423 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
426 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 382 printAndVerify("After Machine Scheduling"); in addOptimizedRegAlloc()
390 printAndVerify("After StackSlotColoring"); in addOptimizedRegAlloc()
396 printAndVerify("After Pre-RegAlloc TailDuplicate"); in addMachineSSAOptimization()
415 printAndVerify("After codegen DCE pass"); in addMachineSSAOptimization()
421 printAndVerify("After ILP optimizations"); in addMachineSSAOptimization()
427 printAndVerify("After Machine LICM, CSE and Sinking passes"); in addMachineSSAOptimization()
430 printAndVerify("After codegen peephole optimization pass"); in addMachineSSAOptimization()
|
| /dports/devel/llvm10/llvm-10.0.1.src/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 68 TPC.printAndVerify(Banner); in addPass()
226 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
229 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 68 TPC.printAndVerify(Banner); in addPass()
226 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
229 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 68 TPC.printAndVerify(Banner); in addPass()
226 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
229 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|
| /dports/devel/llvm11/llvm-11.0.1.src/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 68 TPC.printAndVerify(Banner); in addPass()
226 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
229 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 69 TPC.printAndVerify(Banner); in addPass()
231 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
234 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 69 TPC.printAndVerify(Banner); in addPass()
231 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
234 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/tools/llvm-exegesis/lib/ |
| H A D | Assembler.cpp | 69 TPC.printAndVerify(Banner); in addPass()
231 TPC->printAndVerify("MachineFunctionGenerator::assemble"); in assembleToStream()
234 TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses"); in assembleToStream()
|