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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
H A Dvc4_qpu.c33 set_src_raddr(uint64_t inst, struct qpu_reg src) in set_src_raddr()
81 qpu_a_dst(struct qpu_reg dst) in qpu_a_dst()
98 qpu_m_dst(struct qpu_reg dst) in qpu_m_dst()
115 qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) in qpu_a_MOV()
134 qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) in qpu_m_MOV()
153 qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) in qpu_load_imm_ui()
168 qpu_load_imm_u2(struct qpu_reg dst, uint32_t val) in qpu_load_imm_u2()
175 qpu_load_imm_i2(struct qpu_reg dst, uint32_t val) in qpu_load_imm_i2()
197 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) in qpu_a_alu2()
218 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) in qpu_m_alu2()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
H A Dvc4_qpu.c33 set_src_raddr(uint64_t inst, struct qpu_reg src) in set_src_raddr()
81 qpu_a_dst(struct qpu_reg dst) in qpu_a_dst()
98 qpu_m_dst(struct qpu_reg dst) in qpu_m_dst()
115 qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) in qpu_a_MOV()
134 qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) in qpu_m_MOV()
153 qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) in qpu_load_imm_ui()
168 qpu_load_imm_u2(struct qpu_reg dst, uint32_t val) in qpu_load_imm_u2()
175 qpu_load_imm_i2(struct qpu_reg dst, uint32_t val) in qpu_load_imm_i2()
197 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) in qpu_a_alu2()
218 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) in qpu_m_alu2()
[all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
H A Dvc4_qpu.c33 set_src_raddr(uint64_t inst, struct qpu_reg src) in set_src_raddr()
81 qpu_a_dst(struct qpu_reg dst) in qpu_a_dst()
98 qpu_m_dst(struct qpu_reg dst) in qpu_m_dst()
115 qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) in qpu_a_MOV()
134 qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) in qpu_m_MOV()
153 qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) in qpu_load_imm_ui()
168 qpu_load_imm_u2(struct qpu_reg dst, uint32_t val) in qpu_load_imm_u2()
175 qpu_load_imm_i2(struct qpu_reg dst, uint32_t val) in qpu_load_imm_i2()
197 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) in qpu_a_alu2()
218 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) in qpu_m_alu2()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_qpu.h36 struct qpu_reg { struct
41 static inline struct qpu_reg argument
44 struct qpu_reg r = { in qpu_rn()
52 static inline struct qpu_reg
138 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
139 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
174 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
181 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
[all …]
/dports/lang/clover/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
188 struct qpu_reg *temp_registers) in v3d_generate_code_block()
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
210 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
219 src[i] = qpu_reg(0); in v3d_generate_code_block()
245 struct qpu_reg dst; in v3d_generate_code_block()
[all …]
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/broadcom/compiler/
H A Dvir_to_qpu.c28 static inline struct qpu_reg
29 qpu_reg(int index) in qpu_reg() function
31 struct qpu_reg reg = { in qpu_reg()
38 static inline struct qpu_reg
41 struct qpu_reg reg = { in qpu_magic()
48 static inline struct qpu_reg
194 struct qpu_reg *temp_registers) in v3d_generate_code_block()
211 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
216 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
246 struct qpu_reg dst; in v3d_generate_code_block()
[all …]

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