| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/amd/vulkan/ |
| H A D | radv_meta_fmask_copy.c | 265 if (radv_image_is_tc_compat_cmask(src_image) != radv_image_is_tc_compat_cmask(dst_image)) in radv_can_use_fmask_copy()
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| H A D | radv_image.c | 1072 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1265 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1280 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1472 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2301 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2135 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| H A D | radv_cmd_buffer.c | 1744 if (radv_image_is_tc_compat_cmask(image) && (radv_is_fmask_decompress_pipeline(cmd_buffer) || in radv_emit_fb_color_state()
7471 if (radv_image_is_tc_compat_cmask(image) || in radv_init_color_image_metadata()
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/libosmesa/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| H A D | radv_cmd_buffer.c | 1744 if (radv_image_is_tc_compat_cmask(image) && (radv_is_fmask_decompress_pipeline(cmd_buffer) || in radv_emit_fb_color_state()
7471 if (radv_image_is_tc_compat_cmask(image) || in radv_init_color_image_metadata()
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| /dports/graphics/mesa-dri/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/lang/clover/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_image.c | 1013 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1191 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1206 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1398 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
2192 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
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| H A D | radv_private.h | 2045 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/amd/vulkan/ |
| H A D | radv_image.c | 1087 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1100 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
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| H A D | radv_private.h | 1890 radv_image_is_tc_compat_cmask(const struct radv_image *image) in radv_image_is_tc_compat_cmask() function
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