/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 10 define <vscale x 16 x i1> @rdffr() #0 { 11 ; CHECK-LABEL: rdffr: 13 ; CHECK-NEXT: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 22 ; CHECK-NEXT: rdffr p0.b, p0/z 24 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 28 ; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs. 35 %rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 36 …ut = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr) 66 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 10 define <vscale x 16 x i1> @rdffr() #0 { 11 ; CHECK-LABEL: rdffr: 13 ; CHECK-NEXT: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 22 ; CHECK-NEXT: rdffr p0.b, p0/z 24 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 28 ; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs. 35 %rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 36 …ut = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr) 66 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 10 define <vscale x 16 x i1> @rdffr() #0 { 11 ; CHECK-LABEL: rdffr: 13 ; CHECK-NEXT: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 22 ; CHECK-NEXT: rdffr p0.b, p0/z 24 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 28 ; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs. 35 %rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 36 …ut = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr) 66 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 10 define <vscale x 16 x i1> @rdffr() #0 { 11 ; CHECK-LABEL: rdffr: 13 ; CHECK-NEXT: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 22 ; CHECK-NEXT: rdffr p0.b, p0/z 24 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 28 ; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs. 35 %rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 36 …ut = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr) 66 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 10 define <vscale x 16 x i1> @rdffr() #0 { 11 ; CHECK-LABEL: rdffr: 13 ; CHECK-NEXT: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 22 ; CHECK-NEXT: rdffr p0.b, p0/z 24 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 28 ; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs. 35 %rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 36 …ut = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr) 66 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 11 define <vscale x 16 x i1> @rdffr() { 12 ; CHECK-LABEL: rdffr: 13 ; CHECK: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 21 ; CHECK: rdffr p0.b, p0/z 23 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 51 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 52 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 11 define <vscale x 16 x i1> @rdffr() { 12 ; CHECK-LABEL: rdffr: 13 ; CHECK: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 21 ; CHECK: rdffr p0.b, p0/z 23 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 51 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 52 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 11 define <vscale x 16 x i1> @rdffr() { 12 ; CHECK-LABEL: rdffr: 13 ; CHECK: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 21 ; CHECK: rdffr p0.b, p0/z 23 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 51 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 52 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 11 define <vscale x 16 x i1> @rdffr() { 12 ; CHECK-LABEL: rdffr: 13 ; CHECK: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 21 ; CHECK: rdffr p0.b, p0/z 23 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 51 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 52 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ffr-manipulation.ll | 11 define <vscale x 16 x i1> @rdffr() { 12 ; CHECK-LABEL: rdffr: 13 ; CHECK: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 21 ; CHECK: rdffr p0.b, p0/z 23 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 51 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 52 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm10/llvm-10.0.1.src/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 12 rdffr p0.b label 18 rdffr p15.b label 24 rdffr p0.b, p0/z label 30 rdffr p15.b, p15/z label
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm11/llvm-11.0.1.src/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm90/llvm-9.0.1.src/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm80/llvm-8.0.1.src/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm70/llvm-7.0.1.src/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AArch64/SVE/ |
H A D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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