1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - memory.c *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2002 Hacktarux *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21
22 #include "memory.h"
23
24 #include "../api/m64p_types.h"
25 #include "../api/callbacks.h"
26
27 #include "../main/device.h"
28 #include "../main/main.h"
29
30 #include "../r4300/new_dynarec/new_dynarec.h"
31 #include "../r4300/r4300_core.h"
32
33 #include "../rdp/rdp_core.h"
34 #include "../rsp/rsp_core.h"
35
36 #include "../ai/ai_controller.h"
37 #include "../pi/pi_controller.h"
38 #include "../ri/ri_controller.h"
39 #include "../si/si_controller.h"
40 #include "../vi/vi_controller.h"
41 #include "../dd/dd_controller.h"
42
43 #ifdef DBG
44 #include "../debugger/dbg_types.h"
45 #include "../debugger/dbg_memory.h"
46 #include "../debugger/dbg_breakpoints.h"
47
48 #include <string.h>
49 #endif
50
51 #include <stddef.h>
52 #include <stdint.h>
53
54 #if NEW_DYNAREC < NEW_DYNAREC_ARM
55 // address : address of the read/write operation being done
56 uint32_t address = 0;
57 #endif
58
59 // values that are being written are stored in these variables
60 #if NEW_DYNAREC < NEW_DYNAREC_ARM
61 uint32_t cpu_word;
62 uint8_t cpu_byte;
63 uint16_t cpu_hword;
64 uint64_t cpu_dword;
65 #endif
66
67 // address where the read value will be stored
68 uint64_t* rdword;
69
70 // hash tables of read functions
71 void (*readmem[0x10000])(void);
72 void (*readmemb[0x10000])(void);
73 void (*readmemh[0x10000])(void);
74 void (*readmemd[0x10000])(void);
75
76 // hash tables of write functions
77 void (*writemem[0x10000])(void);
78 void (*writememb[0x10000])(void);
79 void (*writememd[0x10000])(void);
80 void (*writememh[0x10000])(void);
81
82 typedef int (*readfn)(void*,uint32_t,uint32_t*);
83 typedef int (*writefn)(void*,uint32_t,uint32_t,uint32_t);
84
85 #ifndef BYTE4_XOR_BE
86 #ifdef MSB_FIRST
87 #define BYTE4_XOR_BE(a) (a)
88 #else
89 #define BYTE4_XOR_BE(a) ((a) ^ 3)
90 #endif
91 #endif
92
93 #ifndef BSHIFT
94 #define BSHIFT(a) (BYTE4_XOR_BE((a & 3)) << 3)
95 #endif
96
97 #ifndef HSHIFT
98 #define HSHIFT(a) (((a & 2) ^ 2) << 3)
99 #endif
100
readb(readfn read_word,void * opaque,uint32_t address,uint64_t * value)101 static int readb(readfn read_word, void* opaque, uint32_t address, uint64_t* value)
102 {
103 uint32_t w;
104 unsigned shift = BSHIFT(address);
105 int result = read_word(opaque, address, &w);
106 *value = (w >> shift) & 0xff;
107 return result;
108 }
109
readh(readfn read_word,void * opaque,uint32_t address,uint64_t * value)110 static int readh(readfn read_word, void* opaque, uint32_t address, uint64_t* value)
111 {
112 uint32_t w;
113 unsigned shift = HSHIFT(address);
114 int result = read_word(opaque, address, &w);
115 *value = (w >> shift) & 0xffff;
116 return result;
117 }
118
readw(readfn read_word,void * opaque,uint32_t address,uint64_t * value)119 static int readw(readfn read_word, void* opaque, uint32_t address, uint64_t* value)
120 {
121 uint32_t w;
122 int result = read_word(opaque, address, &w);
123 *value = w;
124 return result;
125 }
126
readd(readfn read_word,void * opaque,uint32_t address,uint64_t * value)127 static int readd(readfn read_word, void* opaque, uint32_t address, uint64_t* value)
128 {
129 uint32_t w[2];
130 int result =
131 read_word(opaque, address , &w[0]);
132 read_word(opaque, address + 4, &w[1]);
133 *value = ((uint64_t)w[0] << 32) | w[1];
134 return result;
135 }
136
writeb(writefn write_word,void * opaque,uint32_t address,uint8_t value)137 static int writeb(writefn write_word, void *opaque, uint32_t address, uint8_t value)
138 {
139 unsigned int shift = BSHIFT(address);
140 uint32_t w = (uint32_t)value << shift;
141 uint32_t mask = (uint32_t)0xff << shift;
142 return write_word(opaque, address, w, mask);
143 }
144
writeh(writefn write_word,void * opaque,uint32_t address,uint16_t value)145 static int writeh(writefn write_word, void *opaque, uint32_t address, uint16_t value)
146 {
147 unsigned int shift = HSHIFT(address);
148 uint32_t w = (uint32_t)value << shift;
149 uint32_t mask = (uint32_t)0xffff << shift;
150 return write_word(opaque, address, w, mask);
151 }
152
writew(writefn write_word,void * opaque,uint32_t address,uint32_t value)153 static int writew(writefn write_word, void *opaque, uint32_t address, uint32_t value)
154 {
155 return write_word(opaque, address, value, ~0U);
156 }
157
writed(writefn write_word,void * opaque,uint32_t address,uint64_t value)158 static int writed(writefn write_word, void *opaque, uint32_t address, uint64_t value)
159 {
160 int result;
161 const uint64_t doubleword = (uint64_t)value;
162 const uint32_t word_hi = (uint32_t)(doubleword >> 32);
163 const uint32_t word_lo = (uint32_t)(doubleword >> 0);
164
165 result =
166 write_word(opaque, address + 0, word_hi, ~0U);
167 write_word (opaque, address + 4, word_lo, ~0U);
168 return result;
169 }
170
read_nothing(void)171 static void read_nothing(void)
172 {
173 *rdword = 0;
174 }
175
read_nothingb(void)176 static void read_nothingb(void)
177 {
178 *rdword = 0;
179 }
180
read_nothingh(void)181 static void read_nothingh(void)
182 {
183 *rdword = 0;
184 }
185
read_nothingd(void)186 static void read_nothingd(void)
187 {
188 *rdword = 0;
189 }
190
write_nothing(void)191 static void write_nothing(void)
192 {
193 }
194
write_nothingb(void)195 static void write_nothingb(void)
196 {
197 }
198
write_nothingh(void)199 static void write_nothingh(void)
200 {
201 }
202
write_nothingd(void)203 static void write_nothingd(void)
204 {
205 }
206
read_nomem(void)207 static void read_nomem(void)
208 {
209 address = virtual_to_physical_address(&g_dev.r4300, address,0);
210 if (address == 0x00000000) return;
211 read_word_in_memory();
212 }
213
read_nomemb(void)214 static void read_nomemb(void)
215 {
216 address = virtual_to_physical_address(&g_dev.r4300, address,0);
217 if (address == 0x00000000) return;
218 read_byte_in_memory();
219 }
220
read_nomemh(void)221 static void read_nomemh(void)
222 {
223 address = virtual_to_physical_address(&g_dev.r4300, address,0);
224 if (address == 0x00000000) return;
225 read_hword_in_memory();
226 }
227
read_nomemd(void)228 static void read_nomemd(void)
229 {
230 address = virtual_to_physical_address(&g_dev.r4300, address,0);
231 if (address == 0x00000000) return;
232 read_dword_in_memory();
233 }
234
write_nomem(void)235 static void write_nomem(void)
236 {
237 invalidate_r4300_cached_code(address, 4);
238 address = virtual_to_physical_address(&g_dev.r4300, address,1);
239 if (address == 0x00000000) return;
240 write_word_in_memory();
241 }
242
write_nomemb(void)243 static void write_nomemb(void)
244 {
245 invalidate_r4300_cached_code(address, 1);
246 address = virtual_to_physical_address(&g_dev.r4300, address,1);
247 if (address == 0x00000000) return;
248 write_byte_in_memory();
249 }
250
write_nomemh(void)251 static void write_nomemh(void)
252 {
253 invalidate_r4300_cached_code(address, 2);
254 address = virtual_to_physical_address(&g_dev.r4300, address,1);
255 if (address == 0x00000000) return;
256 write_hword_in_memory();
257 }
258
write_nomemd(void)259 static void write_nomemd(void)
260 {
261 invalidate_r4300_cached_code(address, 8);
262 address = virtual_to_physical_address(&g_dev.r4300, address,1);
263 if (address == 0x00000000) return;
264 write_dword_in_memory();
265 }
266
267
read_rdram(void)268 void read_rdram(void)
269 {
270 readw(read_rdram_dram, &g_dev.ri, address, rdword);
271 }
272
read_rdramb(void)273 void read_rdramb(void)
274 {
275 readb(read_rdram_dram, &g_dev.ri, address, rdword);
276 }
277
read_rdramh(void)278 void read_rdramh(void)
279 {
280 readh(read_rdram_dram, &g_dev.ri, address, rdword);
281 }
282
read_rdramd(void)283 void read_rdramd(void)
284 {
285 readd(read_rdram_dram, &g_dev.ri, address, rdword);
286 }
287
write_rdram(void)288 void write_rdram(void)
289 {
290 writew(write_rdram_dram, &g_dev.ri, address, cpu_word);
291 }
292
write_rdramb(void)293 void write_rdramb(void)
294 {
295 writeb(write_rdram_dram, &g_dev.ri, address, cpu_byte);
296 }
297
write_rdramh(void)298 void write_rdramh(void)
299 {
300 writeh(write_rdram_dram, &g_dev.ri, address, cpu_hword);
301 }
302
write_rdramd(void)303 void write_rdramd(void)
304 {
305 writed(write_rdram_dram, &g_dev.ri, address, cpu_dword);
306 }
307
308
read_rdramFB(void)309 void read_rdramFB(void)
310 {
311 readw(read_rdram_fb, &g_dev.dp, address, rdword);
312 }
313
read_rdramFBb(void)314 void read_rdramFBb(void)
315 {
316 readb(read_rdram_fb, &g_dev.dp, address, rdword);
317 }
318
read_rdramFBh(void)319 void read_rdramFBh(void)
320 {
321 readh(read_rdram_fb, &g_dev.dp, address, rdword);
322 }
323
read_rdramFBd(void)324 void read_rdramFBd(void)
325 {
326 readd(read_rdram_fb, &g_dev.dp, address, rdword);
327 }
328
write_rdramFB(void)329 void write_rdramFB(void)
330 {
331 writew(write_rdram_fb, &g_dev.dp, address, cpu_word);
332 }
333
write_rdramFBb(void)334 void write_rdramFBb(void)
335 {
336 writeb(write_rdram_fb, &g_dev.dp, address, cpu_byte);
337 }
338
write_rdramFBh(void)339 void write_rdramFBh(void)
340 {
341 writeh(write_rdram_fb, &g_dev.dp, address, cpu_hword);
342 }
343
write_rdramFBd(void)344 void write_rdramFBd(void)
345 {
346 writed(write_rdram_fb, &g_dev.dp, address, cpu_dword);
347 }
348
349
read_rdramreg(void)350 static void read_rdramreg(void)
351 {
352 readw(read_rdram_regs, &g_dev.ri, address, rdword);
353 }
354
read_rdramregb(void)355 static void read_rdramregb(void)
356 {
357 readb(read_rdram_regs, &g_dev.ri, address, rdword);
358 }
359
read_rdramregh(void)360 static void read_rdramregh(void)
361 {
362 readh(read_rdram_regs, &g_dev.ri, address, rdword);
363 }
364
read_rdramregd(void)365 static void read_rdramregd(void)
366 {
367 readd(read_rdram_regs, &g_dev.ri, address, rdword);
368 }
369
write_rdramreg(void)370 static void write_rdramreg(void)
371 {
372 writew(write_rdram_regs, &g_dev.ri, address, cpu_word);
373 }
374
write_rdramregb(void)375 static void write_rdramregb(void)
376 {
377 writeb(write_rdram_regs, &g_dev.ri, address, cpu_byte);
378 }
379
write_rdramregh(void)380 static void write_rdramregh(void)
381 {
382 writeh(write_rdram_regs, &g_dev.ri, address, cpu_hword);
383 }
384
write_rdramregd(void)385 static void write_rdramregd(void)
386 {
387 writed(write_rdram_regs, &g_dev.ri, address, cpu_dword);
388 }
389
390
read_rspmem(void)391 static void read_rspmem(void)
392 {
393 readw(read_rsp_mem, &g_dev.sp, address, rdword);
394 }
395
read_rspmemb(void)396 static void read_rspmemb(void)
397 {
398 readb(read_rsp_mem, &g_dev.sp, address, rdword);
399 }
400
read_rspmemh(void)401 static void read_rspmemh(void)
402 {
403 readh(read_rsp_mem, &g_dev.sp, address, rdword);
404 }
405
read_rspmemd(void)406 static void read_rspmemd(void)
407 {
408 readd(read_rsp_mem, &g_dev.sp, address, rdword);
409 }
410
write_rspmem(void)411 static void write_rspmem(void)
412 {
413 writew(write_rsp_mem, &g_dev.sp, address, cpu_word);
414 }
415
write_rspmemb(void)416 static void write_rspmemb(void)
417 {
418 writeb(write_rsp_mem, &g_dev.sp, address, cpu_byte);
419 }
420
write_rspmemh(void)421 static void write_rspmemh(void)
422 {
423 writeh(write_rsp_mem, &g_dev.sp, address, cpu_hword);
424 }
425
write_rspmemd(void)426 static void write_rspmemd(void)
427 {
428 writed(write_rsp_mem, &g_dev.sp, address, cpu_dword);
429 }
430
431
read_rspreg(void)432 static void read_rspreg(void)
433 {
434 readw(read_rsp_regs, &g_dev.sp, address, rdword);
435 }
436
read_rspregb(void)437 static void read_rspregb(void)
438 {
439 readb(read_rsp_regs, &g_dev.sp, address, rdword);
440 }
441
read_rspregh(void)442 static void read_rspregh(void)
443 {
444 readh(read_rsp_regs, &g_dev.sp, address, rdword);
445 }
446
read_rspregd(void)447 static void read_rspregd(void)
448 {
449 readd(read_rsp_regs, &g_dev.sp, address, rdword);
450 }
451
write_rspreg(void)452 static void write_rspreg(void)
453 {
454 writew(write_rsp_regs, &g_dev.sp, address, cpu_word);
455 }
456
write_rspregb(void)457 static void write_rspregb(void)
458 {
459 writeb(write_rsp_regs, &g_dev.sp, address, cpu_byte);
460 }
461
write_rspregh(void)462 static void write_rspregh(void)
463 {
464 writeh(write_rsp_regs, &g_dev.sp, address, cpu_hword);
465 }
466
write_rspregd(void)467 static void write_rspregd(void)
468 {
469 writed(write_rsp_regs, &g_dev.sp, address, cpu_dword);
470 }
471
472
read_rspreg2(void)473 static void read_rspreg2(void)
474 {
475 readw(read_rsp_regs2, &g_dev.sp, address, rdword);
476 }
477
read_rspreg2b(void)478 static void read_rspreg2b(void)
479 {
480 readb(read_rsp_regs2, &g_dev.sp, address, rdword);
481 }
482
read_rspreg2h(void)483 static void read_rspreg2h(void)
484 {
485 readh(read_rsp_regs2, &g_dev.sp, address, rdword);
486 }
487
read_rspreg2d(void)488 static void read_rspreg2d(void)
489 {
490 readd(read_rsp_regs2, &g_dev.sp, address, rdword);
491 }
492
write_rspreg2(void)493 static void write_rspreg2(void)
494 {
495 writew(write_rsp_regs2, &g_dev.sp, address, cpu_word);
496 }
497
write_rspreg2b(void)498 static void write_rspreg2b(void)
499 {
500 writeb(write_rsp_regs2, &g_dev.sp, address, cpu_byte);
501 }
502
write_rspreg2h(void)503 static void write_rspreg2h(void)
504 {
505 writeh(write_rsp_regs2, &g_dev.sp, address, cpu_hword);
506 }
507
write_rspreg2d(void)508 static void write_rspreg2d(void)
509 {
510 writed(write_rsp_regs2, &g_dev.sp, address, cpu_dword);
511 }
512
513
read_dp(void)514 static void read_dp(void)
515 {
516 readw(read_dpc_regs, &g_dev.dp, address, rdword);
517 }
518
read_dpb(void)519 static void read_dpb(void)
520 {
521 readb(read_dpc_regs, &g_dev.dp, address, rdword);
522 }
523
read_dph(void)524 static void read_dph(void)
525 {
526 readh(read_dpc_regs, &g_dev.dp, address, rdword);
527 }
528
read_dpd(void)529 static void read_dpd(void)
530 {
531 readd(read_dpc_regs, &g_dev.dp, address, rdword);
532 }
533
write_dp(void)534 static void write_dp(void)
535 {
536 writew(write_dpc_regs, &g_dev.dp, address, cpu_word);
537 }
538
write_dpb(void)539 static void write_dpb(void)
540 {
541 writeb(write_dpc_regs, &g_dev.dp, address, cpu_byte);
542 }
543
write_dph(void)544 static void write_dph(void)
545 {
546 writeh(write_dpc_regs, &g_dev.dp, address, cpu_hword);
547 }
548
write_dpd(void)549 static void write_dpd(void)
550 {
551 writed(write_dpc_regs, &g_dev.dp, address, cpu_dword);
552 }
553
554
read_dps(void)555 static void read_dps(void)
556 {
557 readw(read_dps_regs, &g_dev.dp, address, rdword);
558 }
559
read_dpsb(void)560 static void read_dpsb(void)
561 {
562 readb(read_dps_regs, &g_dev.dp, address, rdword);
563 }
564
read_dpsh(void)565 static void read_dpsh(void)
566 {
567 readh(read_dps_regs, &g_dev.dp, address, rdword);
568 }
569
read_dpsd(void)570 static void read_dpsd(void)
571 {
572 readd(read_dps_regs, &g_dev.dp, address, rdword);
573 }
574
write_dps(void)575 static void write_dps(void)
576 {
577 writew(write_dps_regs, &g_dev.dp, address, cpu_word);
578 }
579
write_dpsb(void)580 static void write_dpsb(void)
581 {
582 writeb(write_dps_regs, &g_dev.dp, address, cpu_byte);
583 }
584
write_dpsh(void)585 static void write_dpsh(void)
586 {
587 writeh(write_dps_regs, &g_dev.dp, address, cpu_hword);
588 }
589
write_dpsd(void)590 static void write_dpsd(void)
591 {
592 writed(write_dps_regs, &g_dev.dp, address, cpu_dword);
593 }
594
595
read_mi(void)596 static void read_mi(void)
597 {
598 readw(read_mi_regs, &g_dev.r4300, address, rdword);
599 }
600
read_mib(void)601 static void read_mib(void)
602 {
603 readb(read_mi_regs, &g_dev.r4300, address, rdword);
604 }
605
read_mih(void)606 static void read_mih(void)
607 {
608 readh(read_mi_regs, &g_dev.r4300, address, rdword);
609 }
610
read_mid(void)611 static void read_mid(void)
612 {
613 readd(read_mi_regs, &g_dev.r4300, address, rdword);
614 }
615
write_mi(void)616 void write_mi(void)
617 {
618 writew(write_mi_regs, &g_dev.r4300, address, cpu_word);
619 }
620
write_mib(void)621 void write_mib(void)
622 {
623 writeb(write_mi_regs, &g_dev.r4300, address, cpu_byte);
624 }
625
write_mih(void)626 void write_mih(void)
627 {
628 writeh(write_mi_regs, &g_dev.r4300, address, cpu_hword);
629 }
630
write_mid(void)631 void write_mid(void)
632 {
633 writed(write_mi_regs, &g_dev.r4300, address, cpu_dword);
634 }
635
636
read_vi(void)637 static void read_vi(void)
638 {
639 readw(read_vi_regs, &g_dev.vi, address, rdword);
640 }
641
read_vib(void)642 static void read_vib(void)
643 {
644 readb(read_vi_regs, &g_dev.vi, address, rdword);
645 }
646
read_vih(void)647 static void read_vih(void)
648 {
649 readh(read_vi_regs, &g_dev.vi, address, rdword);
650 }
651
read_vid(void)652 static void read_vid(void)
653 {
654 readd(read_vi_regs, &g_dev.vi, address, rdword);
655 }
656
write_vi(void)657 static void write_vi(void)
658 {
659 writew(write_vi_regs, &g_dev.vi, address, cpu_word);
660 }
661
write_vib(void)662 static void write_vib(void)
663 {
664 writeb(write_vi_regs, &g_dev.vi, address, cpu_byte);
665 }
666
write_vih(void)667 static void write_vih(void)
668 {
669 writeh(write_vi_regs, &g_dev.vi, address, cpu_hword);
670 }
671
write_vid(void)672 static void write_vid(void)
673 {
674 writed(write_vi_regs, &g_dev.vi, address, cpu_dword);
675 }
676
677
read_ai(void)678 static void read_ai(void)
679 {
680 readw(read_ai_regs, &g_dev.ai, address, rdword);
681 }
682
read_aib(void)683 static void read_aib(void)
684 {
685 readb(read_ai_regs, &g_dev.ai, address, rdword);
686 }
687
read_aih(void)688 static void read_aih(void)
689 {
690 readh(read_ai_regs, &g_dev.ai, address, rdword);
691 }
692
read_aid(void)693 static void read_aid(void)
694 {
695 readd(read_ai_regs, &g_dev.ai, address, rdword);
696 }
697
write_ai(void)698 static void write_ai(void)
699 {
700 writew(write_ai_regs, &g_dev.ai, address, cpu_word);
701 }
702
write_aib(void)703 static void write_aib(void)
704 {
705 writeb(write_ai_regs, &g_dev.ai, address, cpu_byte);
706 }
707
write_aih(void)708 static void write_aih(void)
709 {
710 writeh(write_ai_regs, &g_dev.ai, address, cpu_hword);
711 }
712
write_aid(void)713 static void write_aid(void)
714 {
715 writed(write_ai_regs, &g_dev.ai, address, cpu_dword);
716 }
717
718
read_pi(void)719 static void read_pi(void)
720 {
721 readw(read_pi_regs, &g_dev.pi, address, rdword);
722 }
723
read_pib(void)724 static void read_pib(void)
725 {
726 readb(read_pi_regs, &g_dev.pi, address, rdword);
727 }
728
read_pih(void)729 static void read_pih(void)
730 {
731 readh(read_pi_regs, &g_dev.pi, address, rdword);
732 }
733
read_pid(void)734 static void read_pid(void)
735 {
736 readd(read_pi_regs, &g_dev.pi, address, rdword);
737 }
738
write_pi(void)739 static void write_pi(void)
740 {
741 writew(write_pi_regs, &g_dev.pi, address, cpu_word);
742 }
743
write_pib(void)744 static void write_pib(void)
745 {
746 writeb(write_pi_regs, &g_dev.pi, address, cpu_byte);
747 }
748
write_pih(void)749 static void write_pih(void)
750 {
751 writeh(write_pi_regs, &g_dev.pi, address, cpu_hword);
752 }
753
write_pid(void)754 static void write_pid(void)
755 {
756 writed(write_pi_regs, &g_dev.pi, address, cpu_dword);
757 }
758
759
read_ri(void)760 static void read_ri(void)
761 {
762 readw(read_ri_regs, &g_dev.ri, address, rdword);
763 }
764
read_rib(void)765 static void read_rib(void)
766 {
767 readb(read_ri_regs, &g_dev.ri, address, rdword);
768 }
769
read_rih(void)770 static void read_rih(void)
771 {
772 readh(read_ri_regs, &g_dev.ri, address, rdword);
773 }
774
read_rid(void)775 static void read_rid(void)
776 {
777 readd(read_ri_regs, &g_dev.ri, address, rdword);
778 }
779
write_ri(void)780 static void write_ri(void)
781 {
782 writew(write_ri_regs, &g_dev.ri, address, cpu_word);
783 }
784
write_rib(void)785 static void write_rib(void)
786 {
787 writeb(write_ri_regs, &g_dev.ri, address, cpu_byte);
788 }
789
write_rih(void)790 static void write_rih(void)
791 {
792 writeh(write_ri_regs, &g_dev.ri, address, cpu_hword);
793 }
794
write_rid(void)795 static void write_rid(void)
796 {
797 writed(write_ri_regs, &g_dev.ri, address, cpu_dword);
798 }
799
800
read_si(void)801 static void read_si(void)
802 {
803 readw(read_si_regs, &g_dev.si, address, rdword);
804 }
805
read_sib(void)806 static void read_sib(void)
807 {
808 readb(read_si_regs, &g_dev.si, address, rdword);
809 }
810
read_sih(void)811 static void read_sih(void)
812 {
813 readh(read_si_regs, &g_dev.si, address, rdword);
814 }
815
read_sid(void)816 static void read_sid(void)
817 {
818 readd(read_si_regs, &g_dev.si, address, rdword);
819 }
820
write_si(void)821 static void write_si(void)
822 {
823 writew(write_si_regs, &g_dev.si, address, cpu_word);
824 }
825
write_sib(void)826 static void write_sib(void)
827 {
828 writeb(write_si_regs, &g_dev.si, address, cpu_byte);
829 }
830
write_sih(void)831 static void write_sih(void)
832 {
833 writeh(write_si_regs, &g_dev.si, address, cpu_hword);
834 }
835
write_sid(void)836 static void write_sid(void)
837 {
838 writed(write_si_regs, &g_dev.si, address, cpu_dword);
839 }
840
read_pi_flashram_status(void)841 static void read_pi_flashram_status(void)
842 {
843 readw(read_flashram_status, &g_dev.pi, address, rdword);
844 }
845
read_pi_flashram_statusb(void)846 static void read_pi_flashram_statusb(void)
847 {
848 readb(read_flashram_status, &g_dev.pi, address, rdword);
849 }
850
read_pi_flashram_statush(void)851 static void read_pi_flashram_statush(void)
852 {
853 readh(read_flashram_status, &g_dev.pi, address, rdword);
854 }
855
read_pi_flashram_statusd(void)856 static void read_pi_flashram_statusd(void)
857 {
858 readd(read_flashram_status, &g_dev.pi, address, rdword);
859 }
860
write_pi_flashram_command(void)861 static void write_pi_flashram_command(void)
862 {
863 writew(write_flashram_command, &g_dev.pi, address, cpu_word);
864 }
865
write_pi_flashram_commandb(void)866 static void write_pi_flashram_commandb(void)
867 {
868 writeb(write_flashram_command, &g_dev.pi, address, cpu_byte);
869 }
870
write_pi_flashram_commandh(void)871 static void write_pi_flashram_commandh(void)
872 {
873 writeh(write_flashram_command, &g_dev.pi, address, cpu_hword);
874 }
875
write_pi_flashram_commandd(void)876 static void write_pi_flashram_commandd(void)
877 {
878 writed(write_flashram_command, &g_dev.pi, address, cpu_dword);
879 }
880
881
read_rom(void)882 static void read_rom(void)
883 {
884 readw(read_cart_rom, &g_dev.pi, address, rdword);
885 }
886
read_romb(void)887 static void read_romb(void)
888 {
889 readb(read_cart_rom, &g_dev.pi, address, rdword);
890 }
891
read_romh(void)892 static void read_romh(void)
893 {
894 readh(read_cart_rom, &g_dev.pi, address, rdword);
895 }
896
read_romd(void)897 static void read_romd(void)
898 {
899 readd(read_cart_rom, &g_dev.pi, address, rdword);
900 }
901
write_rom(void)902 static void write_rom(void)
903 {
904 writew(write_cart_rom, &g_dev.pi, address, cpu_word);
905 }
906
907
read_pif(void)908 static void read_pif(void)
909 {
910 readw(read_pif_ram, &g_dev.si, address, rdword);
911 }
912
read_pifb(void)913 static void read_pifb(void)
914 {
915 readb(read_pif_ram, &g_dev.si, address, rdword);
916 }
917
read_pifh(void)918 static void read_pifh(void)
919 {
920 readh(read_pif_ram, &g_dev.si, address, rdword);
921 }
922
read_pifd(void)923 static void read_pifd(void)
924 {
925 readd(read_pif_ram, &g_dev.si, address, rdword);
926 }
927
write_pif(void)928 static void write_pif(void)
929 {
930 writew(write_pif_ram, &g_dev.si, address, cpu_word);
931 }
932
write_pifb(void)933 static void write_pifb(void)
934 {
935 writeb(write_pif_ram, &g_dev.si, address, cpu_byte);
936 }
937
write_pifh(void)938 static void write_pifh(void)
939 {
940 writeh(write_pif_ram, &g_dev.si, address, cpu_hword);
941 }
942
write_pifd(void)943 static void write_pifd(void)
944 {
945 writed(write_pif_ram, &g_dev.si, address, cpu_dword);
946 }
947
read_dd(void)948 static void read_dd(void)
949 {
950 readw(read_dd_regs, &g_dev.dd, address, rdword);
951 }
952
read_ddb(void)953 static void read_ddb(void)
954 {
955 readb(read_dd_regs, &g_dev.dd, address, rdword);
956 }
957
read_ddh(void)958 static void read_ddh(void)
959 {
960 readh(read_dd_regs, &g_dev.dd, address, rdword);
961 }
962
read_ddd(void)963 static void read_ddd(void)
964 {
965 readd(read_dd_regs, &g_dev.dd, address, rdword);
966 }
967
write_dd(void)968 static void write_dd(void)
969 {
970 writew(write_dd_regs, &g_dev.dd, address, cpu_word);
971 }
972
write_ddb(void)973 static void write_ddb(void)
974 {
975 writeb(write_dd_regs, &g_dev.dd, address, cpu_byte);
976 }
977
write_ddh(void)978 static void write_ddh(void)
979 {
980 writeh(write_dd_regs, &g_dev.dd, address, cpu_hword);
981 }
982
write_ddd(void)983 static void write_ddd(void)
984 {
985 writed(write_dd_regs, &g_dev.dd, address, cpu_dword);
986 }
987
read_ddipl(void)988 static void read_ddipl(void)
989 {
990 readw(read_dd_ipl, &g_dev.pi, address, rdword);
991 }
992
read_ddiplb(void)993 static void read_ddiplb(void)
994 {
995 readb(read_dd_ipl, &g_dev.pi, address, rdword);
996 }
997
read_ddiplh(void)998 static void read_ddiplh(void)
999 {
1000 readh(read_dd_ipl, &g_dev.pi, address, rdword);
1001 }
1002
read_ddipld(void)1003 static void read_ddipld(void)
1004 {
1005 readd(read_dd_ipl, &g_dev.pi, address, rdword);
1006 }
1007
write_ddipl(void)1008 static void write_ddipl(void)
1009 {
1010 writew(write_dd_ipl, &g_dev.pi, address, cpu_word);
1011 }
1012
1013 #ifdef DBG
1014 static int memtype[0x10000];
1015 static void (*saved_readmemb[0x10000])(void);
1016 static void (*saved_readmemh[0x10000])(void);
1017 static void (*saved_readmem [0x10000])(void);
1018 static void (*saved_readmemd[0x10000])(void);
1019 static void (*saved_writememb[0x10000])(void);
1020 static void (*saved_writememh[0x10000])(void);
1021 static void (*saved_writemem [0x10000])(void);
1022 static void (*saved_writememd[0x10000])(void);
1023
readmemb_with_bp_checks(void)1024 static void readmemb_with_bp_checks(void)
1025 {
1026 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 1,
1027 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_READ);
1028
1029 saved_readmemb[address>>16]();
1030 }
1031
readmemh_with_bp_checks(void)1032 static void readmemh_with_bp_checks(void)
1033 {
1034 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 2,
1035 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_READ);
1036
1037 saved_readmemh[address>>16]();
1038 }
1039
readmem_with_bp_checks(void)1040 static void readmem_with_bp_checks(void)
1041 {
1042 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 4,
1043 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_READ);
1044
1045 saved_readmem[address>>16]();
1046 }
1047
readmemd_with_bp_checks(void)1048 static void readmemd_with_bp_checks(void)
1049 {
1050 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 8,
1051 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_READ);
1052
1053 saved_readmemd[address>>16]();
1054 }
1055
writememb_with_bp_checks(void)1056 static void writememb_with_bp_checks(void)
1057 {
1058 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 1,
1059 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_WRITE);
1060
1061 return saved_writememb[address>>16]();
1062 }
1063
writememh_with_bp_checks(void)1064 static void writememh_with_bp_checks(void)
1065 {
1066 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 2,
1067 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_WRITE);
1068
1069 return saved_writememh[address>>16]();
1070 }
1071
writemem_with_bp_checks(void)1072 static void writemem_with_bp_checks(void)
1073 {
1074 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 4,
1075 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_WRITE);
1076
1077 return saved_writemem[address>>16]();
1078 }
1079
writememd_with_bp_checks(void)1080 static void writememd_with_bp_checks(void)
1081 {
1082 check_breakpoints_on_mem_access((*r4300_pc())-0x4, address, 8,
1083 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_WRITE);
1084
1085 return saved_writememd[address>>16]();
1086 }
1087
activate_memory_break_read(uint32_t address)1088 void activate_memory_break_read(uint32_t address)
1089 {
1090 uint16_t region = address >> 16;
1091
1092 if (saved_readmem[region] != NULL)
1093 return;
1094
1095 saved_readmemb[region] = readmemb[region];
1096 saved_readmemh[region] = readmemh[region];
1097 saved_readmem [region] = readmem [region];
1098 saved_readmemd[region] = readmemd[region];
1099 readmemb[region] = readmemb_with_bp_checks;
1100 readmemh[region] = readmemh_with_bp_checks;
1101 readmem [region] = readmem_with_bp_checks;
1102 readmemd[region] = readmemd_with_bp_checks;
1103 }
1104
deactivate_memory_break_read(uint32_t address)1105 void deactivate_memory_break_read(uint32_t address)
1106 {
1107 uint16_t region = address >> 16;
1108
1109 if (saved_readmem[region] == NULL)
1110 return;
1111
1112 readmemb[region] = saved_readmemb[region];
1113 readmemh[region] = saved_readmemh[region];
1114 readmem [region] = saved_readmem [region];
1115 readmemd[region] = saved_readmemd[region];
1116 saved_readmemb[region] = NULL;
1117 saved_readmemh[region] = NULL;
1118 saved_readmem [region] = NULL;
1119 saved_readmemd[region] = NULL;
1120 }
1121
activate_memory_break_write(uint32_t address)1122 void activate_memory_break_write(uint32_t address)
1123 {
1124 uint16_t region = address >> 16;
1125
1126 if (saved_writemem[region] != NULL)
1127 return;
1128
1129 saved_writememb[region] = writememb[region];
1130 saved_writememh[region] = writememh[region];
1131 saved_writemem [region] = writemem [region];
1132 saved_writememd[region] = writememd[region];
1133 writememb[region] = writememb_with_bp_checks;
1134 writememh[region] = writememh_with_bp_checks;
1135 writemem [region] = writemem_with_bp_checks;
1136 writememd[region] = writememd_with_bp_checks;
1137 }
1138
deactivate_memory_break_write(uint32_t address)1139 void deactivate_memory_break_write(uint32_t address)
1140 {
1141 uint16_t region = address >> 16;
1142
1143 if (saved_writemem[region] == NULL)
1144 return;
1145
1146 writememb[region] = saved_writememb[region];
1147 writememh[region] = saved_writememh[region];
1148 writemem [region] = saved_writemem [region];
1149 writememd[region] = saved_writememd[region];
1150 saved_writememb[region] = NULL;
1151 saved_writememh[region] = NULL;
1152 saved_writemem [region] = NULL;
1153 saved_writememd[region] = NULL;
1154 }
1155
get_memory_type(uint32_t address)1156 int get_memory_type(uint32_t address)
1157 {
1158 return memtype[address >> 16];
1159 }
1160 #endif
1161
1162 #define R(x) read_ ## x ## b, read_ ## x ## h, read_ ## x, read_ ## x ## d
1163 #define W(x) write_ ## x ## b, write_ ## x ## h, write_ ## x, write_ ## x ## d
1164 #define RW(x) R(x), W(x)
1165
poweron_memory(void)1166 void poweron_memory(void)
1167 {
1168 int i;
1169
1170 #ifdef DBG
1171 memset(saved_readmem, 0, 0x10000*sizeof(saved_readmem[0]));
1172 memset(saved_writemem, 0, 0x10000*sizeof(saved_writemem[0]));
1173 #endif
1174
1175 /* clear mappings */
1176 for (i = 0; i < 0x10000; ++i)
1177 {
1178 map_region(i, M64P_MEM_NOMEM, RW(nomem));
1179 }
1180
1181 /* map RDRAM */
1182 for (i = 0; i< 0x80; ++i)
1183 {
1184 map_region(0x8000+i, M64P_MEM_RDRAM, RW(rdram));
1185 map_region(0xa000+i, M64P_MEM_RDRAM, RW(rdram));
1186 }
1187
1188 for(i = 0x80; i < 0x3f0; ++i)
1189 {
1190 map_region(0x8000+i, M64P_MEM_NOTHING, RW(nothing));
1191 map_region(0xa000+i, M64P_MEM_NOTHING, RW(nothing));
1192 }
1193
1194 /* map RDRAM registers */
1195 map_region(0x83f0, M64P_MEM_RDRAMREG, RW(rdramreg));
1196 map_region(0xa3f0, M64P_MEM_RDRAMREG, RW(rdramreg));
1197 for(i = 1; i < 0x10; ++i)
1198 {
1199 map_region(0x83f0+i, M64P_MEM_NOTHING, RW(nothing));
1200 map_region(0xa3f0+i, M64P_MEM_NOTHING, RW(nothing));
1201 }
1202
1203 /* map RSP memory */
1204 map_region(0x8400, M64P_MEM_RSPMEM, RW(rspmem));
1205 map_region(0xa400, M64P_MEM_RSPMEM, RW(rspmem));
1206 for (i=0x1; i<0x4; i++)
1207 {
1208 map_region(0x8400+i, M64P_MEM_NOTHING, RW(nothing));
1209 map_region(0xa400+i, M64P_MEM_NOTHING, RW(nothing));
1210 }
1211
1212 /* map RSP registers (1) */
1213 map_region(0x8404, M64P_MEM_RSPREG, RW(rspreg));
1214 map_region(0xa404, M64P_MEM_RSPREG, RW(rspreg));
1215 for (i=0x5; i<0x8; i++)
1216 {
1217 map_region(0x8400+i, M64P_MEM_NOTHING, RW(nothing));
1218 map_region(0xa400+i, M64P_MEM_NOTHING, RW(nothing));
1219 }
1220
1221 /* map RSP registers (2) */
1222 map_region(0x8408, M64P_MEM_RSP, RW(rspreg2));
1223 map_region(0xa408, M64P_MEM_RSP, RW(rspreg2));
1224
1225 for(i = 0x9; i < 0x10; ++i)
1226 {
1227 map_region(0x8400+i, M64P_MEM_NOTHING, RW(nothing));
1228 map_region(0xa400+i, M64P_MEM_NOTHING, RW(nothing));
1229 }
1230
1231 /* map DPC registers */
1232 map_region(0x8410, M64P_MEM_DP, RW(dp));
1233 map_region(0xa410, M64P_MEM_DP, RW(dp));
1234 for(i = 1; i < 0x10; ++i)
1235 {
1236 map_region(0x8410+i, M64P_MEM_NOTHING, RW(nothing));
1237 map_region(0xa410+i, M64P_MEM_NOTHING, RW(nothing));
1238 }
1239
1240 map_region(0x8420, M64P_MEM_DPS, RW(dps));
1241 map_region(0xa420, M64P_MEM_DPS, RW(dps));
1242 for(i = 1; i < 0x10; ++i)
1243 {
1244 map_region(0x8420+i, M64P_MEM_NOTHING, RW(nothing));
1245 map_region(0xa420+i, M64P_MEM_NOTHING, RW(nothing));
1246 }
1247
1248 /* map MI registers */
1249 map_region(0x8430, M64P_MEM_MI, RW(mi));
1250 map_region(0xa430, M64P_MEM_MI, RW(mi));
1251
1252 for(i = 1; i < 0x10; ++i)
1253 {
1254 map_region(0x8430+i, M64P_MEM_NOTHING, RW(nothing));
1255 map_region(0xa430+i, M64P_MEM_NOTHING, RW(nothing));
1256 }
1257
1258 /* map VI registers */
1259 map_region(0x8440, M64P_MEM_VI, RW(vi));
1260 map_region(0xa440, M64P_MEM_VI, RW(vi));
1261 for(i = 1; i < 0x10; ++i)
1262 {
1263 map_region(0x8440+i, M64P_MEM_NOTHING, RW(nothing));
1264 map_region(0xa440+i, M64P_MEM_NOTHING, RW(nothing));
1265 }
1266
1267 /* map AI registers */
1268 map_region(0x8450, M64P_MEM_AI, RW(ai));
1269 map_region(0xa450, M64P_MEM_AI, RW(ai));
1270
1271 for(i = 1; i < 0x10; ++i)
1272 {
1273 map_region(0x8450+i, M64P_MEM_NOTHING, RW(nothing));
1274 map_region(0xa450+i, M64P_MEM_NOTHING, RW(nothing));
1275 }
1276
1277 /* map PI registers */
1278
1279 map_region(0x8460, M64P_MEM_PI, RW(pi));
1280 map_region(0xa460, M64P_MEM_PI, RW(pi));
1281 for(i = 1; i < 0x10; ++i)
1282 {
1283 map_region(0x8460+i, M64P_MEM_NOTHING, RW(nothing));
1284 map_region(0xa460+i, M64P_MEM_NOTHING, RW(nothing));
1285 }
1286
1287 /* map RI registers */
1288 map_region(0x8470, M64P_MEM_RI, RW(ri));
1289 map_region(0xa470, M64P_MEM_RI, RW(ri));
1290 for(i = 1; i < 0x10; ++i)
1291 {
1292 map_region(0x8470+i, M64P_MEM_NOTHING, RW(nothing));
1293 map_region(0xa470+i, M64P_MEM_NOTHING, RW(nothing));
1294 }
1295
1296 /* map SI registers */
1297 map_region(0x8480, M64P_MEM_SI, RW(si));
1298 map_region(0xa480, M64P_MEM_SI, RW(si));
1299 for(i = 0x481; i < 0x500; ++i)
1300 {
1301 map_region(0x8000+i, M64P_MEM_NOTHING, RW(nothing));
1302 map_region(0xa000+i, M64P_MEM_NOTHING, RW(nothing));
1303 }
1304
1305 /* map DD registers */
1306 map_region(0x8500, M64P_MEM_DD, RW(dd));
1307 map_region(0xa500, M64P_MEM_DD, RW(dd));
1308 for(i = 0x501; i < 0x600; ++i)
1309 {
1310 map_region(0x8000+i, M64P_MEM_NOTHING, RW(nothing));
1311 map_region(0xa000+i, M64P_MEM_NOTHING, RW(nothing));
1312 }
1313
1314 /* map DD IPL ROM */
1315 for (i = 0x600; i < 0x640; ++i)
1316 {
1317 map_region(0x8000 + i, M64P_MEM_DD, R(ddipl), W(nothing));
1318 map_region(0xa000 + i, M64P_MEM_DD, R(ddipl), W(nothing));
1319 }
1320 for (i = 0x640; i < 0x800; ++i)
1321 {
1322 map_region(0x8000 + i, M64P_MEM_NOTHING, RW(nothing));
1323 map_region(0xa000 + i, M64P_MEM_NOTHING, RW(nothing));
1324 }
1325
1326 /* map flashram/sram */
1327 map_region(0x8800, M64P_MEM_FLASHRAMSTAT, R(pi_flashram_status), W(nothing));
1328 map_region(0xa800, M64P_MEM_FLASHRAMSTAT, R(pi_flashram_status), W(nothing));
1329 map_region(0x8801, M64P_MEM_NOTHING, R(nothing), W(pi_flashram_command));
1330 map_region(0xa801, M64P_MEM_NOTHING, R(nothing), W(pi_flashram_command));
1331 for(i = 0x802; i < 0x1000; ++i)
1332 {
1333 map_region(0x8000+i, M64P_MEM_NOTHING, RW(nothing));
1334 map_region(0xa000+i, M64P_MEM_NOTHING, RW(nothing));
1335 }
1336
1337 /* map cart ROM */
1338
1339 for(i = 0; i < (g_dev.pi.cart_rom.rom_size >> 16); ++i)
1340 {
1341 map_region(0x9000+i, M64P_MEM_ROM, R(rom), W(nothing));
1342 map_region(0xb000+i, M64P_MEM_ROM, R(rom),
1343 write_nothingb, write_nothingh, write_rom, write_nothingd);
1344 }
1345 for(i = (g_dev.pi.cart_rom.rom_size >> 16); i < 0xfc0; ++i)
1346 {
1347 map_region(0x9000+i, M64P_MEM_NOTHING, RW(nothing));
1348 map_region(0xb000+i, M64P_MEM_NOTHING, RW(nothing));
1349 }
1350
1351 /* map PIF RAM */
1352 map_region(0x9fc0, M64P_MEM_PIF, RW(pif));
1353 map_region(0xbfc0, M64P_MEM_PIF, RW(pif));
1354 for(i = 0xfc1; i < 0x1000; ++i)
1355 {
1356 map_region(0x9000+i, M64P_MEM_NOTHING, RW(nothing));
1357 map_region(0xb000+i, M64P_MEM_NOTHING, RW(nothing));
1358 }
1359 }
1360
map_region_t(uint16_t region,int type)1361 static void map_region_t(uint16_t region, int type)
1362 {
1363 #ifdef DBG
1364 memtype[region] = type;
1365 #else
1366 (void)region;
1367 (void)type;
1368 #endif
1369 }
1370
map_region_r(uint16_t region,void (* read8)(void),void (* read16)(void),void (* read32)(void),void (* read64)(void))1371 static void map_region_r(uint16_t region,
1372 void (*read8)(void),
1373 void (*read16)(void),
1374 void (*read32)(void),
1375 void (*read64)(void))
1376 {
1377 #ifdef DBG
1378 if (lookup_breakpoint(((uint32_t)region << 16), 0x10000,
1379 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_READ) != -1)
1380 {
1381 saved_readmemb[region] = read8;
1382 saved_readmemh[region] = read16;
1383 saved_readmem [region] = read32;
1384 saved_readmemd[region] = read64;
1385 readmemb[region] = readmemb_with_bp_checks;
1386 readmemh[region] = readmemh_with_bp_checks;
1387 readmem [region] = readmem_with_bp_checks;
1388 readmemd[region] = readmemd_with_bp_checks;
1389 }
1390 else
1391 #endif
1392 {
1393 readmemb[region] = read8;
1394 readmemh[region] = read16;
1395 readmem [region] = read32;
1396 readmemd[region] = read64;
1397 }
1398 }
1399
map_region_w(uint16_t region,void (* write8)(void),void (* write16)(void),void (* write32)(void),void (* write64)(void))1400 void map_region_w(uint16_t region,
1401 void (*write8)(void),
1402 void (*write16)(void),
1403 void (*write32)(void),
1404 void (*write64)(void))
1405 {
1406 #ifdef DBG
1407 if (lookup_breakpoint(((uint32_t)region << 16), 0x10000,
1408 M64P_BKP_FLAG_ENABLED | M64P_BKP_FLAG_WRITE) != -1)
1409 {
1410 saved_writememb[region] = write8;
1411 saved_writememh[region] = write16;
1412 saved_writemem [region] = write32;
1413 saved_writememd[region] = write64;
1414 writememb[region] = writememb_with_bp_checks;
1415 writememh[region] = writememh_with_bp_checks;
1416 writemem [region] = writemem_with_bp_checks;
1417 writememd[region] = writememd_with_bp_checks;
1418 }
1419 else
1420 #endif
1421 {
1422 writememb[region] = write8;
1423 writememh[region] = write16;
1424 writemem [region] = write32;
1425 writememd[region] = write64;
1426 }
1427 }
1428
map_region(uint16_t region,int type,void (* read8)(void),void (* read16)(void),void (* read32)(void),void (* read64)(void),void (* write8)(void),void (* write16)(void),void (* write32)(void),void (* write64)(void))1429 void map_region(uint16_t region,
1430 int type,
1431 void (*read8)(void),
1432 void (*read16)(void),
1433 void (*read32)(void),
1434 void (*read64)(void),
1435 void (*write8)(void),
1436 void (*write16)(void),
1437 void (*write32)(void),
1438 void (*write64)(void))
1439 {
1440 map_region_t(region, type);
1441 map_region_r(region, read8, read16, read32, read64);
1442 map_region_w(region, write8, write16, write32, write64);
1443 }
1444
fast_mem_access(uint32_t address)1445 uint32_t *fast_mem_access(uint32_t address)
1446 {
1447 /* This code is performance critical, specially on pure interpreter mode.
1448 * Removing error checking saves some time, but the emulator may crash. */
1449 if ((address & 0xc0000000) != 0x80000000)
1450 address = virtual_to_physical_address(&g_dev.r4300, address, 2);
1451
1452 address &= UINT32_C(0x1ffffffc);
1453
1454 if (address < RDRAM_MAX_SIZE)
1455 return (uint32_t*)((uint8_t*)g_dev.ri.rdram.dram + address);
1456 else if (address >= UINT32_C(0x10000000))
1457 return (uint32_t*)((uint8_t*)g_dev.pi.cart_rom.rom + address - UINT32_C(0x10000000));
1458 else if ((address & UINT32_C(0xffffe000)) == UINT32_C(0x04000000))
1459 return (uint32_t*)((uint8_t*)g_dev.sp.mem + (address & UINT32_C(0x1ffc)));
1460 return NULL;
1461 }
1462