| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1;
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos;
930 read_value |= (u32)benable << rgbgammaemb_bitpos;
937 const u32 rgbgammaemb_bitpos = 1;
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos;
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos);
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|
| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.c | 922 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_set_rgblayer_gamma_enable() local
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
930 read_value |= (u32)benable << rgbgammaemb_bitpos; in nx_mlc_set_rgblayer_gamma_enable()
937 const u32 rgbgammaemb_bitpos = 1; in nx_mlc_get_rgblayer_gamma_enable() local
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; in nx_mlc_get_rgblayer_gamma_enable()
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos); in nx_mlc_get_rgblayer_gamma_enable()
|