| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
353 info->rl_val[cs][idx][C]++; in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
353 info->rl_val[cs][idx][C]++; in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
353 info->rl_val[cs][idx][C]++; in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
353 info->rl_val[cs][idx][C]++; in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
[all …]
|