rsubhn (reference) in projects: dports - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:rsubhn (Results 1 – 25 of 245) sorted by relevance

12 3 4 5 6 7 8 9 10

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
H A D	arm64-vecFold.ll	`111 ; CHECK: rsubhn.8b v0, v0, v1 114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun… 115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no… 144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone`
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AArch64/
H A D	arm64-vsub.ll	66 ;CHECK: rsubhn.8b 69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) 75 ;CHECK: rsubhn.4h 78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) 84 ;CHECK: rsubhn.2s 93 ;CHECK: rsubhn.8b 103 ;CHECK: rsubhn.4h 113 ;CHECK: rsubhn.2s 121 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 122 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]

12 3 4 5 6 7 8 9 10