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Searched refs:rx_tvalid (Results 1 – 19 of 19) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/
H A Db205.v210 wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid; net
254 .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
291 .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
H A Db205_core.v32 output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, port
243 .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/
H A Daxi_stream_to_wb.v40 input rx_tvalid, port
119 .clka(clk_i), .ena(rx_tready), .wea(rx_tvalid),
176 if (rx_tready && rx_tvalid) begin
258 rx_state, rx_tlast, rx_tvalid, rx_tready, rx_tuser[2:0], //8
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/
H A Dfifo64_to_axi4lite.v78 wire rx_tvalid; net
94 .o_tvalid(rx_tvalid),
133 .axi_str_rxd_tvalid(rx_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/
H A Db200.v245 wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid; net
288 .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
353 .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
H A Db200_core.v34 output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, port
267 .o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready));
318 ….rx_tdata(r0_rx_tdata), .rx_tlast(r0_rx_tlast), .rx_tvalid(r0_rx_tvalid), .rx_tready(r0_rx_tready…
350 ….rx_tdata(r1_rx_tdata), .rx_tlast(r1_rx_tlast), .rx_tvalid(r1_rx_tvalid), .rx_tready(r1_rx_tready…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge_interface/
H A Dxge_mac_wrapper.v46 output rx_tvalid, port
310 .m_axis_tvalid(rx_tvalid),
321 assign rx_tvalid = rx_tvalid_int;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/simple_gemac/
H A Dgmii_to_axis.v34 output rx_tvalid, port
170 .m_axis_tvalid(rx_tvalid),
H A Dsimple_gemac_wrapper.v20 … output [63:0] rx_tdata, output [3:0] rx_tuser, output rx_tlast, output rx_tvalid, input rx_tready, port
110 .m_aclk(sys_clk), .m_axis_tvalid(rx_tvalid), .m_axis_tready(rx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/
H A Dten_gig_eth_loopback_tb.sv204 .rx_tvalid(s_rx_chdr.axis.tvalid),
303 .rx_tvalid(loop_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/
H A Done_gig_eth_loopback_tb.sv173 .rx_tvalid(s_rx_chdr.axis.tvalid),
236 .rx_tvalid(loop_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/gpif2/
H A Dgpif2_slave_fifo32.v46 input [63:0] rx_tdata, input rx_tlast, input rx_tvalid, output rx_tready, port
496 .i_tdata(rx_tdata), .i_tlast(rx_tlast), .i_tvalid(rx_tvalid), .i_tready(rx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dsoft_ctrl.v62 input rx_tvalid, port
268 ….i_aclk(clk), .i_tdata({rx_tdata, rx_tuser, rx_tlast}), .i_tvalid(rx_tvalid), .i_tready(rx_tready),
288 .rx_tvalid(rx_tvalid_div2), .rx_tready(rx_tready_div2),
H A Dx300_sfpp_io_core.v177 .rx_tvalid(m_axis_tvalid),
256 .rx_tvalid(m_axis_tvalid),
H A Dbus_int.v287 .rx_tvalid(zpui_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/
H A Darm_to_sfp_tb.sv191 .rx_tvalid(s_axis.axis.tvalid),
304 .rx_tvalid(loop_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dn3xx_mgt_io_core.v329 .rx_tvalid(m_axis_tvalid),
428 .rx_tvalid(m_axis_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_mgt_io_core.v382 .rx_tvalid(m_axis_tvalid),
519 .rx_tvalid(m_axis_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/radio_200/
H A Dradio_legacy.v30 output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, port
113 .o_tdata(rx_tdata), .o_tlast(rx_tlast), .o_tvalid(rx_tvalid), .o_tready(rx_tready));