/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/ |
H A D | e31x_timing.xdc | 140 set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].val… 144 set_false_path -through [get_pins {usr_access_i/DATA[*]}] 149 set_false_path -from [get_ports CAT_CTRL_OUT] 150 set_false_path -to [get_ports CAT_RESET] 151 set_false_path -to [get_ports RX*_BANDSEL*] 152 set_false_path -to [get_ports TX_BANDSEL*] 153 set_false_path -to [get_ports TX_ENABLE*] 154 set_false_path -to [get_ports LED_*] 155 set_false_path -to [get_ports VCRX*] 156 set_false_path -to [get_ports VCTX*] [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vivado_ipi/axi_dmac/ |
H A D | axi_dmac_constr.ttcl | 27 set_false_path -quiet \ 32 set_false_path -quiet \ 69 set_false_path -quiet \ 74 set_false_path -quiet \ 144 set_false_path -quiet \ 149 set_false_path -quiet \ 154 set_false_path -quiet \ 158 set_false_path -quiet \ 162 set_false_path -quiet \ 165 set_false_path -quiet \
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/ |
H A D | chipscope_ila_32.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/ |
H A D | chipscope_ila.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/ |
H A D | chipscope_ila_32.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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H A D | b200_chipscope_ila.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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H A D | chipscope_ila_128.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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H A D | chipscope_ila_256.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/ |
H A D | chipscope_ila.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/ |
H A D | chipscope_ila_256.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/ |
H A D | chipscope_ila_128.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/ |
H A D | b200_chipscope_ila.xdc | 4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa… 5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne… 6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
H A D | n310_aurora.xdc | 11 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/lanes[*].lane_i/mgt_io_i… 13 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_p… 15 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "qsfp_wrapper_i/lanes[*].lane_i/mgt_io_…
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H A D | n310_10ge.xdc | 18 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].l… 19 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].l… 21 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].… 22 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].…
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H A D | n310_1ge.xdc | 13 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige… 14 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige… 15 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/ |
H A D | one_gige_phy.xdc | 153 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/da… 154 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/da… 157 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe… 158 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe… 159 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe… 161 set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] 163 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] 164 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/ |
H A D | one_gige_phy.xdc | 153 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/da… 154 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/da… 157 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe… 158 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe… 159 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe… 161 set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] 163 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] 164 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
H A D | x300_1ge.xdc | 17 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*reset_sync*/PRE}] 18 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe_reg*… 19 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe*[0]/…
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H A D | x300_10ge.xdc | 18 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_… 19 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_…
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H A D | x300_aurora.xdc | 16 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*sfpp_io_*/*/rst_sync_sys_rst_i/*auror…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
H A D | e320_1ge.xdc | 13 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*reset_sy… 14 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_res… 15 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_res…
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H A D | e320_aurora.xdc | 11 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/mgt_io_i/aurora_phy*/aur… 13 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_p…
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H A D | e320_10ge.xdc | 15 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/t… 16 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/t…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/cpld/ |
H A D | Timing.sdc | 40 set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*] 41 set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*] 82 set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}] 83 set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}] 138 set_false_path -from [get_ports {aRxLoLockDetect}] 139 set_false_path -from [get_ports {aTxLoLockDetect}] 145 set_false_path -to [get_ports {aMkReset_n}] 146 set_false_path -to [get_ports {aVcxoCtrl}] 160 set_false_path -to [get_ports {aCh*Led*}]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/cpld/ |
H A D | rhodium_top.sdc | 252 set_false_path -from $ps_csb -to [get_pins *|clrn] 253 set_false_path -from $pl_csb -to [get_pins *|clrn] 258 set_false_path -from $ps_csb -to $ps_rb_out 259 set_false_path -from $pl_csb -to $pl_rb_out 396 set_false_path -to $gpos 397 set_false_path -from $gpis 400 set_false_path -to $lodist_spi_out
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