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Searched refs:set_false_path (Results 1 – 25 of 62) sorted by relevance

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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_timing.xdc140 set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].val…
144 set_false_path -through [get_pins {usr_access_i/DATA[*]}]
149 set_false_path -from [get_ports CAT_CTRL_OUT]
150 set_false_path -to [get_ports CAT_RESET]
151 set_false_path -to [get_ports RX*_BANDSEL*]
152 set_false_path -to [get_ports TX_BANDSEL*]
153 set_false_path -to [get_ports TX_ENABLE*]
154 set_false_path -to [get_ports LED_*]
155 set_false_path -to [get_ports VCRX*]
156 set_false_path -to [get_ports VCTX*]
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vivado_ipi/axi_dmac/
H A Daxi_dmac_constr.ttcl27 set_false_path -quiet \
32 set_false_path -quiet \
69 set_false_path -quiet \
74 set_false_path -quiet \
144 set_false_path -quiet \
149 set_false_path -quiet \
154 set_false_path -quiet \
158 set_false_path -quiet \
162 set_false_path -quiet \
165 set_false_path -quiet \
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/
H A Dchipscope_ila_32.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/
H A Dchipscope_ila.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/
H A Dchipscope_ila_32.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
H A Db200_chipscope_ila.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
H A Dchipscope_ila_128.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
H A Dchipscope_ila_256.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/
H A Dchipscope_ila.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/
H A Dchipscope_ila_256.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/
H A Dchipscope_ila_128.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/
H A Db200_chipscope_ila.xdc4 set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fa…
5 set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_ne…
6 set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_ST…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn310_aurora.xdc11 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/lanes[*].lane_i/mgt_io_i…
13 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_p…
15 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "qsfp_wrapper_i/lanes[*].lane_i/mgt_io_…
H A Dn310_10ge.xdc18 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].l…
19 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].l…
21 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].…
22 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].…
H A Dn310_1ge.xdc13 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
14 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
15 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.xdc153 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/da…
154 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/da…
157 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
158 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
159 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
161 set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
163 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}]
164 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.xdc153 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/da…
154 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/da…
157 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
158 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
159 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
161 set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
163 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}]
164 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_1ge.xdc17 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*reset_sync*/PRE}]
18 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe_reg*…
19 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe*[0]/…
H A Dx300_10ge.xdc18 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_…
19 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_…
H A Dx300_aurora.xdc16 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*sfpp_io_*/*/rst_sync_sys_rst_i/*auror…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A De320_1ge.xdc13 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*reset_sy…
14 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_res…
15 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_res…
H A De320_aurora.xdc11 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/mgt_io_i/aurora_phy*/aur…
13 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_p…
H A De320_10ge.xdc15 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/t…
16 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/t…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/cpld/
H A DTiming.sdc40 set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*]
41 set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*]
82 set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}]
83 set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}]
138 set_false_path -from [get_ports {aRxLoLockDetect}]
139 set_false_path -from [get_ports {aTxLoLockDetect}]
145 set_false_path -to [get_ports {aMkReset_n}]
146 set_false_path -to [get_ports {aVcxoCtrl}]
160 set_false_path -to [get_ports {aCh*Led*}]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/cpld/
H A Drhodium_top.sdc252 set_false_path -from $ps_csb -to [get_pins *|clrn]
253 set_false_path -from $pl_csb -to [get_pins *|clrn]
258 set_false_path -from $ps_csb -to $ps_rb_out
259 set_false_path -from $pl_csb -to $pl_rb_out
396 set_false_path -to $gpos
397 set_false_path -from $gpis
400 set_false_path -to $lodist_spi_out

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