| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 106 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
152 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
153 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
155 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
165 set_pgsection(level1_table, i, in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
176 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 107 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
153 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
154 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
156 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
166 set_pgsection(level1_table, i, in mmu_setup()
173 set_pgsection(level1_table, i, in mmu_setup()
177 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 107 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
153 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
154 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
156 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
166 set_pgsection(level1_table, i, in mmu_setup()
173 set_pgsection(level1_table, i, in mmu_setup()
177 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 107 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
153 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
154 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
156 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
166 set_pgsection(level1_table, i, in mmu_setup()
173 set_pgsection(level1_table, i, in mmu_setup()
177 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 107 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
153 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
154 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
156 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
166 set_pgsection(level1_table, i, in mmu_setup()
173 set_pgsection(level1_table, i, in mmu_setup()
177 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() function
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
172 set_pgsection(level1_table, i, in mmu_setup()
179 set_pgsection(level1_table, i, in mmu_setup()
183 set_pgsection(level1_table, i, in mmu_setup()
|