| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/mips/mach-mtmips/mt7628/ |
| H A D | ddr.c | 70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); in mt7628_ddr_pad_ldo_config()
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); in mt7628_ddr_pad_ldo_config()
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); in mt7628_ddr_pad_ldo_config()
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); in mt7628_ddr_pad_ldo_config()
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); in mt7628_ddr_pad_ldo_config()
|