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Searched refs:shiftamt (Results 1 – 25 of 164) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
H A Dcombine-shl-from-extend-narrow.postlegal.mir125 %shiftamt:_(s32) = G_CONSTANT i32 2
126 %shl:_(s64) = G_SHL %extend, %shiftamt
160 %shiftamt:_(s32) = G_CONSTANT i32 2
161 %shl:_(s64) = G_SHL %extend, %shiftamt
195 %shiftamt:_(s32) = G_CONSTANT i32 2
196 %shl:_(s64) = G_SHL %extend, %shiftamt
231 %shiftamt:_(s32) = G_TRUNC %shiftamt64
232 %shl:_(s64) = G_SHL %extend, %shiftamt
270 %shiftamt:_(s32) = G_CONSTANT i32 2
271 %shl:_(s32) = G_SHL %extend, %shiftamt
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
H A Dcombine-shl-from-extend-narrow.postlegal.mir125 %shiftamt:_(s32) = G_CONSTANT i32 2
126 %shl:_(s64) = G_SHL %extend, %shiftamt
160 %shiftamt:_(s32) = G_CONSTANT i32 2
161 %shl:_(s64) = G_SHL %extend, %shiftamt
195 %shiftamt:_(s32) = G_CONSTANT i32 2
196 %shl:_(s64) = G_SHL %extend, %shiftamt
231 %shiftamt:_(s32) = G_TRUNC %shiftamt64
232 %shl:_(s64) = G_SHL %extend, %shiftamt
270 %shiftamt:_(s32) = G_CONSTANT i32 2
271 %shl:_(s32) = G_SHL %extend, %shiftamt
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
H A Dcombine-shl-from-extend-narrow.prelegal.mir37 %shiftamt:_(s32) = G_CONSTANT i32 2
38 %shl:_(s32) = G_SHL %extend, %shiftamt
74 %shiftamt:_(s32) = G_CONSTANT i32 2
111 %shiftamt:_(s16) = G_CONSTANT i16 2
132 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
143 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
151 %shiftamt:_(s32) = G_CONSTANT i32 2
152 %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
172 ; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
183 ; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-amdgpu-cvt-f32-ubyte.mir17 %shiftamt:_(s32) = G_CONSTANT i32 0
18 %shift:_(s32) = G_LSHR %arg, %shiftamt
36 %shiftamt:_(s32) = G_CONSTANT i32 8
37 %shift:_(s32) = G_LSHR %arg, %shiftamt
55 %shiftamt:_(s32) = G_CONSTANT i32 16
74 %shiftamt:_(s32) = G_CONSTANT i32 24
93 %shiftamt:_(s32) = G_CONSTANT i32 8
112 %shiftamt:_(s32) = G_CONSTANT i32 16
133 %shiftamt:_(s32) = G_CONSTANT i32 24
152 %shiftamt:_(s32) = G_CONSTANT i32 8
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/parisc/math-emu/
H A Ddbl_float.h560 {int shiftamt, sticky; \
561 shiftamt = shift % 32; \
564 case 0: if (shiftamt > 0) { \
567 Dextallp4(srcdstD),shiftamt,Dextallp4(srcdstD)); \
572 Dextallp1(srcdstA) >>= shiftamt; \
575 case 1: if (shiftamt > 0) { \
591 case 2: if (shiftamt > 0) { \
604 case 3: if (shiftamt > 0) { \
763 {int shiftamt, sticky; \
797 shiftamt = (1-exponent) % 32; \
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/parisc/math-emu/
H A Ddbl_float.h560 {int shiftamt, sticky; \
561 shiftamt = shift % 32; \
564 case 0: if (shiftamt > 0) { \
567 Dextallp4(srcdstD),shiftamt,Dextallp4(srcdstD)); \
572 Dextallp1(srcdstA) >>= shiftamt; \
575 case 1: if (shiftamt > 0) { \
591 case 2: if (shiftamt > 0) { \
604 case 3: if (shiftamt > 0) { \
763 {int shiftamt, sticky; \
797 shiftamt = (1-exponent) % 32; \
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/parisc/math-emu/
H A Ddbl_float.h560 {int shiftamt, sticky; \
561 shiftamt = shift % 32; \
564 case 0: if (shiftamt > 0) { \
567 Dextallp4(srcdstD),shiftamt,Dextallp4(srcdstD)); \
572 Dextallp1(srcdstA) >>= shiftamt; \
575 case 1: if (shiftamt > 0) { \
591 case 2: if (shiftamt > 0) { \
604 case 3: if (shiftamt > 0) { \
763 {int shiftamt, sticky; \
797 shiftamt = (1-exponent) % 32; \
[all …]

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