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/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
55 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
57 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
59 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
87 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
89 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
91 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
55 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
57 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
59 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
98 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
53 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
55 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
57 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
85 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
87 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
89 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
53 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
55 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
57 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
93 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
53 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
55 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
57 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
85 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
87 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
89 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
53 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
55 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
57 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
93 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
53 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
55 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
57 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
85 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
87 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
89 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
53 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
55 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
57 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
93 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
55 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
57 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
59 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
87 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
89 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
91 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
65 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
67 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
69 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
163 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
55 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
57 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
59 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
87 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
89 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
91 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
65 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
67 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
69 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
163 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
53 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
55 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
57 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
85 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
87 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
89 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
53 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
55 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
57 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
93 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
137 MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
144 &s_rrr_shi %s shim=0 shty=0
[all …]
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
55 @s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
57 @s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
59 @S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
87 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
89 @s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
91 @S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
55 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
57 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
59 @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
98 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
/dports/math/xlife++/xlifepp-sources-v2.0.1-2018-05-09/src/geometry/
H A DMesh.cpp778 ShapeType shty=_noShape; in Mesh() local
786 if(shty != _noShape && shty != *(sst.begin())) { error("sub_mesh_shap", msh.name_); } in Mesh()
787 else { shty = *(sst.begin()); } in Mesh()
790 if(shty == _noShape) { error("sub_mesh_nodom", msh.name_); } in Mesh()
808 short* xl2sub = (shty==_hexahedron) ? indHex : indId; in Mesh()
822 subdvMesh(msh.nodes, elems, bounds, shty, nbsubdiv, order); in Mesh()

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