Searched refs:sim_verstate (Results 1 – 1 of 1) sorted by relevance
49 static INTBIG sim_verstate; variable206 if (var == NOVARIABLE) sim_verstate = 0; else in sim_writevernetlist()207 sim_verstate = var->addr; in sim_writevernetlist()294 } else if ((sim_verstate&VERILOGUSETRIREG) != 0) in sim_writevernetlist()470 if ((sim_verstate&VERILOGUSEASSIGN) != 0) continue; in sim_verwritecell()570 if ((sim_verstate&VERILOGUSETRIREG) != 0) wiretype = x_("trireg"); else in sim_verwritecell()707 if ((sim_verstate&VERILOGUSEASSIGN) != 0) in sim_verwritecell()