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Searched refs:simd_width (Results 1 – 25 of 96) sorted by relevance

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/dports/math/viennacl/ViennaCL-1.7.1/viennacl/device_specific/templates/
H A Dmatrix_product_template.hpp49 matrix_product_parameters(unsigned int simd_width in matrix_product_parameters()
93 if ((p_.mS % p_.simd_width) > 0 || (p_.nS % p_.simd_width) > 0) in check_invalid_impl()
217 string widthstr = tools::to_string(p.simd_width); in generate_impl()
243 widths[A->name()] = p.simd_width; in generate_impl()
244 widths[B->name()] = p.simd_width; in generate_impl()
588 …lhs_str = "rA[kk][" + tools::to_string(mm/p.simd_width) + "].s" + tools::to_string(mm%p.simd_width… in generate_impl()
592 … rhs_str = "rB[kk]["+tools::to_string(nn/p.simd_width)+"].s"+tools::to_string(nn%p.simd_width); in generate_impl()
641 string Cj = to_string((m/p.simd_width)*(ministride1*p.simd_width) + m%p.simd_width); in generate_impl()
654 …eam << C->process("#pointer += " + to_string((p.local_size_1*p.simd_width) - (p.simd_width-1)) + "… in generate_impl()
673 string Cj = to_string((n/p.simd_width)*(ministride1*p.simd_width) + n%p.simd_width); in generate_impl()
[all …]
H A Dtemplate_base.hpp61 unsigned int simd_width; member
442 std::string strwidth = tools::to_string(simd_width); in element_wise_loop_1D()
450 loop_body(stream, simd_width); in element_wise_loop_1D()
454 if (simd_width>1) in element_wise_loop_1D()
467 if (simd_width==1) in vstore()
470 … return utils::append_width("vstore", simd_width) + "(" + value + ", " + offset + ", " + ptr + ")"; in vstore()
475 if (simd_width==1) in vload()
478 return utils::append_width("vload", simd_width) + "(" + offset + ", " + ptr + ")"; in vload()
581 if (p_.simd_width!=1 && p_.simd_width!=2 && in check_invalid()
582 p_.simd_width!=4 && p_.simd_width!=8 && in check_invalid()
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/dports/databases/arrow/apache-arrow-6.0.1/cpp/src/arrow/util/
H A Dbpacking_simd_codegen.py32 def __init__(self, simd_width): argument
33 self.simd_width = simd_width
34 if simd_width % 32 != 0:
36 self.simd_byte_width = simd_width // 8
149 def main(simd_width): argument
196 gen = UnpackGenerator(simd_width)
219 simd_width = int(sys.argv[1])
223 main(simd_width)
/dports/graphics/embree/embree-3.13.2/kernels/subdiv/
H A Dsubdivpatch1base.cpp16 const int simd_width) in SubdivPatch1Base() argument
57 updateEdgeLevels(edge_level,subdiv,mesh,simd_width); in SubdivPatch1Base()
80 …const float edge_level[4], const int subdiv[4], const SubdivMesh *const mesh, const int simd_width) in updateEdgeLevels() argument
96 grid_size_simd_blocks = ((grid_u_res*grid_v_res+simd_width-1)&(-simd_width)) / simd_width; in updateEdgeLevels()
H A Dsubdivpatch1base.h48 const int simd_width);
60 …onst float edge_level[4], const int subdiv[4], const SubdivMesh *const mesh, const int simd_width);
/dports/www/firefox/firefox-99.0/third_party/intgemm/intgemm/
H A Davx512vnni_gemm.h29 const Index simd_width = width / sizeof(Register); in Multiply() local
34 const Register *B0_col = reinterpret_cast<const Register*>(B) + B0_colidx * simd_width; in Multiply()
39 const Register *A_end = A_live + simd_width; in Multiply()
90 const Index simd_width = width / sizeof(Register); in Multiply8Shift() local
95 const Register *B0_col = reinterpret_cast<const Register*>(B) + B0_colidx * simd_width; in Multiply8Shift()
100 const Register *A_end = A_live + simd_width; in Multiply8Shift()
130 Index simd_width = width / sizeof(Register); in PrepareBias() local
136 const Register *B0_col = reinterpret_cast<const Register*>(B) + B0_colidx * simd_width; in PrepareBias()
138 const Register *B_end = B_live + simd_width*8; in PrepareBias()
H A Dmultiply.h167 const Index simd_width = width / (sizeof(Register) / sizeof(int16_t)); \
171 const Register *B0_col = reinterpret_cast<const Register *>(B) + simd_width * B0_colidx; \
187 for (k = 1; k < simd_width; ++k) { \
224 const Index simd_width = width / (sizeof(Register) / sizeof(int8_t)); \
229 const Register *B0_col = reinterpret_cast<const Register *>(B) + simd_width * B0_colidx; \
252 for (k = 1; k < simd_width; ++k) { \
299 const Index simd_width = width / (sizeof(Register) / sizeof(int8_t)); \
303 const Register *B0_col = reinterpret_cast<const Register *>(B) + simd_width * B0_colidx; \
329 for (k = 1; k < simd_width; ++k) { \
546 const Index simd_width = width / sizeof(Register); \
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/dports/misc/tvm/incubator-tvm-0.6.1/topi/python/topi/x86/
H A Dsparse.py31 simd_width = get_fp32_len()
36 s[outs[0].op].op.axis[1], 2 * simd_width)
54 s[outs[0].op].op.axis[1], 2 * simd_width)
/dports/misc/mxnet/incubator-mxnet-1.9.0/3rdparty/tvm/python/tvm/topi/x86/
H A Dsparse.py30 simd_width = get_fp32_len()
34 (y_o, y_i) = s[outs[0].op].split(s[outs[0].op].op.axis[1], 2 * simd_width)
51 (y_o, y_i) = s[outs[0].op].split(s[outs[0].op].op.axis[1], 2 * simd_width)
/dports/misc/py-tvm/incubator-tvm-0.6.1/topi/python/topi/x86/
H A Dsparse.py31 simd_width = get_fp32_len()
36 s[outs[0].op].op.axis[1], 2 * simd_width)
54 s[outs[0].op].op.axis[1], 2 * simd_width)
/dports/security/vault/vault-1.8.2/vendor/github.com/apache/arrow/rust/arrow/src/compute/
H A Dutil.rs106 simd_width: usize, in is_valid()
112 let simd_upper_bound = i + simd_width; in is_valid()
145 simd_width: usize, in simd_load_set_invalid()
152 let simd_with_zeros = T::load(array.value_slice(i, simd_width)); in simd_load_set_invalid()
154 is_valid::<T>(bitmap, i, simd_width, array.len()), in simd_load_set_invalid()
/dports/graphics/embree/embree-3.13.2/kernels/geometry/
H A Dsubdivpatch1.h35 const int simd_width) in SubdivPatch1()
36 : SubdivPatch1Base(gID,pID,subPatch,mesh,time,uv,edge_level,subdiv,simd_width) {} in SubdivPatch1()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c163 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
165 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
166 simd_width); in lower_cs_intrinsics_convert_block()
H A Dbrw_compiler.h873 unsigned simd_width) in _brw_wm_prog_data_prog_offset() argument
875 switch (simd_width) { in _brw_wm_prog_data_prog_offset()
889 unsigned simd_width) in _brw_wm_prog_data_dispatch_grf_start_reg() argument
891 switch (simd_width) { in _brw_wm_prog_data_dispatch_grf_start_reg()
905 unsigned simd_width) in _brw_wm_prog_data_reg_blocks() argument
907 switch (simd_width) { in _brw_wm_prog_data_reg_blocks()
/dports/lang/clover/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
H A Dbrw_compiler.h977 unsigned simd_width) in _brw_wm_prog_data_prog_offset() argument
979 switch (simd_width) { in _brw_wm_prog_data_prog_offset()
993 unsigned simd_width) in _brw_wm_prog_data_dispatch_grf_start_reg() argument
995 switch (simd_width) { in _brw_wm_prog_data_dispatch_grf_start_reg()
1009 unsigned simd_width) in _brw_wm_prog_data_reg_blocks() argument
1011 switch (simd_width) { in _brw_wm_prog_data_reg_blocks()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c237 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
239 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
240 simd_width); in lower_cs_intrinsics_convert_block()
/dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c229 nir_ssa_def *simd_width = nir_load_simd_width_intel(b); in lower_cs_intrinsics_convert_block() local
231 nir_udiv(b, nir_iadd_imm(b, nir_iadd(b, size, simd_width), -1), in lower_cs_intrinsics_convert_block()
232 simd_width); in lower_cs_intrinsics_convert_block()

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