/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/insns/ |
H A D | vsadd_vi.h | 8 vd = sat_add<int8_t, uint8_t>(vs2, vsext(simm5, sew), sat); 13 vd = sat_add<int16_t, uint16_t>(vs2, vsext(simm5, sew), sat); 18 vd = sat_add<int32_t, uint32_t>(vs2, vsext(simm5, sew), sat); 23 vd = sat_add<int64_t, uint64_t>(vs2, vsext(simm5, sew), sat);
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H A D | vmseq_vi.h | 4 res = simm5 == vs2;
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H A D | vmsgt_vi.h | 4 res = vs2 > simm5;
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H A D | vor_vi.h | 4 vd = simm5 | vs2;
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H A D | vmsle_vi.h | 4 res = vs2 <= simm5;
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H A D | vand_vi.h | 4 vd = simm5 & vs2;
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H A D | vrsub_vi.h | 4 vd = simm5 - vs2;
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H A D | vxor_vi.h | 4 vd = simm5 ^ vs2;
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H A D | vmsne_vi.h | 4 res = vs2 != simm5;
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H A D | vadd_vi.h | 4 vd = simm5 + vs2;
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H A D | vmv_v_i.h | 6 vd = simm5;
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H A D | vsra_vi.h | 4 vd = vs2 >> (simm5 & (sew - 1) & 0x1f);
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H A D | vsll_vi.h | 4 vd = vs2 << (simm5 & (sew - 1) & 0x1f);
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H A D | vmerge_vim.h | 10 vd = use_first ? simm5 : vs2;
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H A D | vssra_vi.h | 5 int sh = simm5 & (sew - 1) & 0x1f;
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H A D | vadc_vim.h | 8 uint128_t res = (op_mask & simm5) + (op_mask & vs2) + carry;
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H A D | vmadc_vim.h | 9 uint128_t res = (op_mask & simm5) + (op_mask & vs2) + carry;
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVSDPatterns.td | 35 // Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants 124 Operand ImmType = simm5> 223 SplatPat_simm5, simm5, swap>; 240 SplatPat_simm5, simm5, swap>; 317 vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.SEW)>; 405 def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1), 408 vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>; 503 def : Pat<(vti.Vector (splat_vector simm5:$rs1)), 505 simm5:$rs1, vti.AVL, vti.SEW)>; 522 def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)), [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVSDPatterns.td | 35 // Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants 124 Operand ImmType = simm5> 223 SplatPat_simm5, simm5, swap>; 240 SplatPat_simm5, simm5, swap>; 317 vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.SEW)>; 405 def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1), 408 vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>; 503 def : Pat<(vti.Vector (splat_vector simm5:$rs1)), 505 simm5:$rs1, vti.AVL, vti.SEW)>; 522 def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)), [all …]
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/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/sparc/ |
H A D | cbcond-diag.s | 3 cwbe %o1, +32,1f ! Overflow in the simm5 field.
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/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/sparc/ |
H A D | cbcond-diag.s | 3 cwbe %o1, +32,1f ! Overflow in the simm5 field.
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/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/sparc/ |
H A D | cbcond-diag.s | 3 cwbe %o1, +32,1f ! Overflow in the simm5 field.
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVSDPatterns.td | 39 // Give explicit Complexity to prefer simm5/uimm5. 154 Operand ImmType = simm5> 246 SplatPat_simm5, simm5, swap>; 263 SplatPat_simm5, simm5, swap>; 271 (vti.Vector (splatpat_kind simm5:$rs2)), 273 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 402 def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), 405 vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; 538 vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.Log2SEW)>; 777 def : Pat<(vti.Vector (SplatPat_simm5 simm5:$rs1)), [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVSDPatterns.td | 39 // Give explicit Complexity to prefer simm5/uimm5. 154 Operand ImmType = simm5> 246 SplatPat_simm5, simm5, swap>; 263 SplatPat_simm5, simm5, swap>; 271 (vti.Vector (splatpat_kind simm5:$rs2)), 273 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 402 def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), 405 vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; 538 vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.Log2SEW)>; 777 def : Pat<(vti.Vector (SplatPat_simm5 simm5:$rs1)), [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVSDPatterns.td | 39 // Give explicit Complexity to prefer simm5/uimm5. 154 Operand ImmType = simm5> 246 SplatPat_simm5, simm5, swap>; 263 SplatPat_simm5, simm5, swap>; 271 (vti.Vector (splatpat_kind simm5:$rs2)), 273 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 402 def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), 405 vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; 538 vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.Log2SEW)>; 777 def : Pat<(vti.Vector (SplatPat_simm5 simm5:$rs1)), [all …]
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