Searched refs:smu7_force_clock_level (Results 1 – 3 of 3) sorted by relevance
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 171 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
3203 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in smu7_force_dpm_level()
3204 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
3205 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); in smu7_force_dpm_level()
4843 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, in smu7_force_clock_level() function
5559 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); in smu7_patch_compute_profile_mode()
5562 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_patch_compute_profile_mode()
5706 .force_clock_level = smu7_force_clock_level,
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 171 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
3203 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in smu7_force_dpm_level()
3204 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
3205 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); in smu7_force_dpm_level()
4843 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, in smu7_force_clock_level() function
5559 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); in smu7_patch_compute_profile_mode()
5562 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_patch_compute_profile_mode()
5706 .force_clock_level = smu7_force_clock_level,
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 171 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
3203 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in smu7_force_dpm_level()
3204 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
3205 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); in smu7_force_dpm_level()
4843 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, in smu7_force_clock_level() function
5559 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); in smu7_patch_compute_profile_mode()
5562 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_patch_compute_profile_mode()
5706 .force_clock_level = smu7_force_clock_level,
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