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Searched refs:spi_ss_sel (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/rtl/verilog/
H A Dspi_top16.v76 wire spi_ss_sel; // ss register select net
89 assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
156 else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
H A Dspi_top.v97 wire spi_ss_sel; // ss register select net
110 assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
240 else if(spi_ss_sel && wb_we_i && !tip)
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/rtl/verilog/
H A Dspi_top16.v78 wire spi_ss_sel; // ss register select net
91 assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
158 else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
H A Dspi_top.v99 wire spi_ss_sel; // ss register select net
112 assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
242 else if(spi_ss_sel && wb_we_i && !tip)