| /dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/ |
| H A D | reload1.c | 173 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
6367 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
6439 spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
6970 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) in do_input_reload()
6977 spill_reg_stored_to[REGNO (rl->reg_rtx)]) in do_input_reload()
6978 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], in do_input_reload()
7013 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
7258 spill_reg_stored_to[i] = out; in emit_reload_insns()
7436 spill_reg_stored_to[src_regno + nr] = out; in emit_reload_insns()
7749 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/ |
| H A D | reload1.c | 163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
6240 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
6313 spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
6839 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) in do_input_reload()
6846 spill_reg_stored_to[REGNO (rl->reg_rtx)]) in do_input_reload()
6847 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], in do_input_reload()
6882 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
7106 spill_reg_stored_to[i] = out; in emit_reload_insns()
7275 spill_reg_stored_to[src_regno + nr] = out; in emit_reload_insns()
7539 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| H A D | ChangeLog.1 | 9781 spill_reg_store and spill_reg_stored_to values are cleared.
11056 (spill_reg_stored_to): New array.
11094 Set / use spill_reg_stored_to.
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/ |
| H A D | reload1.c | 163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
6240 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
6313 spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
6839 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) in do_input_reload()
6846 spill_reg_stored_to[REGNO (rl->reg_rtx)]) in do_input_reload()
6847 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], in do_input_reload()
6882 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
7106 spill_reg_stored_to[i] = out; in emit_reload_insns()
7275 spill_reg_stored_to[src_regno + nr] = out; in emit_reload_insns()
7539 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7129 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7130 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7246 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7839 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7844 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7903 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8145 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8349 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8650 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7132 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7133 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7249 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7842 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7847 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7906 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8148 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8352 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8653 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7132 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7133 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7249 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7842 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7847 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7906 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8148 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8352 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8653 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7132 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7133 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7249 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7842 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7847 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7906 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8148 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8352 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8653 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7234 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7235 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7944 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7949 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8008 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8250 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8468 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8776 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7133 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7134 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7250 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7843 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7848 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7907 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8149 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8353 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8654 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7234 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7235 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7944 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7949 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8008 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8250 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8468 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8776 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/ |
| H A D | reload1.c | 144 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7262 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7263 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7379 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7972 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7977 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8036 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8282 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8498 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8811 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc48/gcc-4.8.5/gcc/ |
| H A D | reload1.c | 148 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7203 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7204 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7314 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7905 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7910 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7969 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8215 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8430 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8745 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7234 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7235 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7944 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7949 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8008 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8250 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8468 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8776 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7234 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7235 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7944 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7949 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8008 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8250 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8468 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8776 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/ |
| H A D | reload1.c | 148 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7269 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7270 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7389 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7980 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7985 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8044 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8290 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8505 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8820 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7234 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7235 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7944 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7949 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8008 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8250 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8468 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8776 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7248 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7249 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7365 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7958 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7963 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8022 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8264 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8484 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8792 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7133 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7134 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7250 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7843 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7848 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7907 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8149 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8353 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8654 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7248 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7249 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7365 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7958 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7963 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8022 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8264 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8484 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8792 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7234 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7235 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7944 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7949 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8008 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8250 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8468 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8776 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
[all …]
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/ |
| H A D | reload1.c | 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7133 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7134 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7250 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7843 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7848 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7907 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8149 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8353 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8654 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
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| /dports/lang/gcc9/gcc-9.4.0/gcc/ |
| H A D | reload1.c | 145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7248 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7249 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7365 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7958 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7963 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8022 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8264 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8484 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8792 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
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| /dports/devel/mingw32-gcc/gcc-4.8.1/gcc/ |
| H A D | reload1.c | 148 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7203 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7204 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7314 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7905 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7910 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7969 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8215 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8430 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8745 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
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| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/ |
| H A D | reload1.c | 144 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; variable
7262 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) in emit_input_reload_insns()
7263 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], in emit_input_reload_insns()
7379 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; in emit_input_reload_insns()
7972 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
7977 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) in do_input_reload()
8036 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) in do_output_reload()
8282 spill_reg_stored_to[regno] = out; in emit_reload_insns()
8498 spill_reg_stored_to[src_regno + k] = out; in emit_reload_insns()
8811 rtx reg = spill_reg_stored_to[last_reload_reg]; in delete_output_reload()
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