Home
last modified time | relevance | path

Searched refs:spu_writech (Results 1 – 25 of 68) sorted by relevance

123

/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/platforms/cell/spufs/
H A Dspu_save.c59 spu_writech(MFC_LSA, ls); in save_upper_240kb()
61 spu_writech(MFC_EAL, list); in save_upper_240kb()
62 spu_writech(MFC_Size, size); in save_upper_240kb()
63 spu_writech(MFC_TagID, tag_id); in save_upper_240kb()
64 spu_writech(MFC_Cmd, cmd); in save_upper_240kb()
115 spu_writech(MFC_LSA, ls); in spill_regs_to_mem()
118 spu_writech(MFC_Size, size); in spill_regs_to_mem()
119 spu_writech(MFC_TagID, tag_id); in spill_regs_to_mem()
120 spu_writech(MFC_Cmd, cmd); in spill_regs_to_mem()
131 spu_writech(MFC_TagID, tag_id); in enqueue_sync()
[all …]
H A Dspu_restore.c39 spu_writech(MFC_LSA, ls); in fetch_regs_from_mem()
42 spu_writech(MFC_Size, size); in fetch_regs_from_mem()
43 spu_writech(MFC_TagID, tag_id); in fetch_regs_from_mem()
44 spu_writech(MFC_Cmd, cmd); in fetch_regs_from_mem()
59 spu_writech(MFC_LSA, ls); in restore_upper_240kb()
61 spu_writech(MFC_EAL, list); in restore_upper_240kb()
62 spu_writech(MFC_Size, size); in restore_upper_240kb()
63 spu_writech(MFC_TagID, tag_id); in restore_upper_240kb()
64 spu_writech(MFC_Cmd, cmd); in restore_upper_240kb()
83 spu_writech(SPU_WrDec, decr); in restore_decr()
[all …]
H A Dspu_utils.h63 spu_writech(SPU_WrEventMask, event_mask); in set_event_mask()
75 spu_writech(MFC_WrTagMask, tag_mask); in set_tag_mask()
110 spu_writech(MFC_LSA, ls); in enqueue_putllc()
111 spu_writech(MFC_EAH, lscsa_ea.ui[0]); in enqueue_putllc()
112 spu_writech(MFC_EAL, lscsa_ea.ui[1]); in enqueue_putllc()
113 spu_writech(MFC_Size, size); in enqueue_putllc()
114 spu_writech(MFC_TagID, tag_id); in enqueue_putllc()
115 spu_writech(MFC_Cmd, cmd); in enqueue_putllc()
126 spu_writech(MFC_WrTagUpdate, update_any); in set_tag_update()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/platforms/cell/spufs/
H A Dspu_save.c59 spu_writech(MFC_LSA, ls); in save_upper_240kb()
61 spu_writech(MFC_EAL, list); in save_upper_240kb()
62 spu_writech(MFC_Size, size); in save_upper_240kb()
63 spu_writech(MFC_TagID, tag_id); in save_upper_240kb()
64 spu_writech(MFC_Cmd, cmd); in save_upper_240kb()
115 spu_writech(MFC_LSA, ls); in spill_regs_to_mem()
118 spu_writech(MFC_Size, size); in spill_regs_to_mem()
119 spu_writech(MFC_TagID, tag_id); in spill_regs_to_mem()
120 spu_writech(MFC_Cmd, cmd); in spill_regs_to_mem()
131 spu_writech(MFC_TagID, tag_id); in enqueue_sync()
[all …]
H A Dspu_restore.c39 spu_writech(MFC_LSA, ls); in fetch_regs_from_mem()
42 spu_writech(MFC_Size, size); in fetch_regs_from_mem()
43 spu_writech(MFC_TagID, tag_id); in fetch_regs_from_mem()
44 spu_writech(MFC_Cmd, cmd); in fetch_regs_from_mem()
59 spu_writech(MFC_LSA, ls); in restore_upper_240kb()
61 spu_writech(MFC_EAL, list); in restore_upper_240kb()
62 spu_writech(MFC_Size, size); in restore_upper_240kb()
63 spu_writech(MFC_TagID, tag_id); in restore_upper_240kb()
64 spu_writech(MFC_Cmd, cmd); in restore_upper_240kb()
83 spu_writech(SPU_WrDec, decr); in restore_decr()
[all …]
H A Dspu_utils.h63 spu_writech(SPU_WrEventMask, event_mask); in set_event_mask()
75 spu_writech(MFC_WrTagMask, tag_mask); in set_tag_mask()
110 spu_writech(MFC_LSA, ls); in enqueue_putllc()
111 spu_writech(MFC_EAH, lscsa_ea.ui[0]); in enqueue_putllc()
112 spu_writech(MFC_EAL, lscsa_ea.ui[1]); in enqueue_putllc()
113 spu_writech(MFC_Size, size); in enqueue_putllc()
114 spu_writech(MFC_TagID, tag_id); in enqueue_putllc()
115 spu_writech(MFC_Cmd, cmd); in enqueue_putllc()
126 spu_writech(MFC_WrTagUpdate, update_any); in set_tag_update()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/platforms/cell/spufs/
H A Dspu_save.c59 spu_writech(MFC_LSA, ls); in save_upper_240kb()
61 spu_writech(MFC_EAL, list); in save_upper_240kb()
62 spu_writech(MFC_Size, size); in save_upper_240kb()
63 spu_writech(MFC_TagID, tag_id); in save_upper_240kb()
64 spu_writech(MFC_Cmd, cmd); in save_upper_240kb()
115 spu_writech(MFC_LSA, ls); in spill_regs_to_mem()
118 spu_writech(MFC_Size, size); in spill_regs_to_mem()
119 spu_writech(MFC_TagID, tag_id); in spill_regs_to_mem()
120 spu_writech(MFC_Cmd, cmd); in spill_regs_to_mem()
131 spu_writech(MFC_TagID, tag_id); in enqueue_sync()
[all …]
H A Dspu_restore.c39 spu_writech(MFC_LSA, ls); in fetch_regs_from_mem()
42 spu_writech(MFC_Size, size); in fetch_regs_from_mem()
43 spu_writech(MFC_TagID, tag_id); in fetch_regs_from_mem()
44 spu_writech(MFC_Cmd, cmd); in fetch_regs_from_mem()
59 spu_writech(MFC_LSA, ls); in restore_upper_240kb()
61 spu_writech(MFC_EAL, list); in restore_upper_240kb()
62 spu_writech(MFC_Size, size); in restore_upper_240kb()
63 spu_writech(MFC_TagID, tag_id); in restore_upper_240kb()
64 spu_writech(MFC_Cmd, cmd); in restore_upper_240kb()
83 spu_writech(SPU_WrDec, decr); in restore_decr()
[all …]
H A Dspu_utils.h63 spu_writech(SPU_WrEventMask, event_mask); in set_event_mask()
75 spu_writech(MFC_WrTagMask, tag_mask); in set_tag_mask()
110 spu_writech(MFC_LSA, ls); in enqueue_putllc()
111 spu_writech(MFC_EAH, lscsa_ea.ui[0]); in enqueue_putllc()
112 spu_writech(MFC_EAL, lscsa_ea.ui[1]); in enqueue_putllc()
113 spu_writech(MFC_Size, size); in enqueue_putllc()
114 spu_writech(MFC_TagID, tag_id); in enqueue_putllc()
115 spu_writech(MFC_Cmd, cmd); in enqueue_putllc()
126 spu_writech(MFC_WrTagUpdate, update_any); in set_tag_update()
/dports/devel/tinygo/tinygo-0.14.1/lib/picolibc/newlib/libc/machine/spu/
H A Dspu_timer_internal.h85 spu_writech (SPU_WrEventMask, mask & ~MFC_DECREMENTER_EVENT); in __disable_spu_decr()
86 spu_writech (SPU_WrEventAck, MFC_DECREMENTER_EVENT); in __disable_spu_decr()
95 spu_writech (SPU_WrDec, (val)); in __enable_spu_decr()
96 spu_writech (SPU_WrEventMask, mask | MFC_DECREMENTER_EVENT); in __enable_spu_decr()
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/newlib/libc/machine/spu/
H A Dspu_timer_internal.h85 spu_writech (SPU_WrEventMask, mask & ~MFC_DECREMENTER_EVENT); in __disable_spu_decr()
86 spu_writech (SPU_WrEventAck, MFC_DECREMENTER_EVENT); in __disable_spu_decr()
95 spu_writech (SPU_WrDec, (val)); in __enable_spu_decr()
96 spu_writech (SPU_WrEventMask, mask | MFC_DECREMENTER_EVENT); in __enable_spu_decr()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gcc9/gcc-9.4.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gcc48/gcc-4.8.5/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gcc8/gcc-8.5.0/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/spu/
H A Dspu_mfcio.h232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)

123