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Searched refs:sreg (Results 1 – 25 of 2064) sorted by relevance

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/dports/lang/sdcc/sdcc-4.0.0/sim/ucsim/avr.src/
H A Darith_inst.cc57 sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C|BIT_Z); in cpi_Rd_K()
59 sreg|= BIT_H; in cpi_Rd_K()
72 sreg|= BIT_S; in cpi_Rd_K()
74 sreg|= BIT_Z; in cpi_Rd_K()
76 sreg|= BIT_C; in cpi_Rd_K()
108 sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C); in sbci_Rd_K()
110 sreg|= BIT_H; in sbci_Rd_K()
243 sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C); in cpc_Rd_Rr()
294 sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C); in sbc_Rd_Rr()
647 sreg|= BIT_Z; in inc_Rd()
[all …]
/dports/lang/mono/mono-5.10.1.57/mono/arch/arm/
H A Darm_vfpmacros.h91 #define ARM_CPYD(p,dreg,sreg) ARM_CPYD_COND(p,dreg,sreg,ARMCOND_AL) argument
95 #define ARM_CPYS(p,dreg,sreg) ARM_CPYS_COND(p,dreg,sreg,ARMCOND_AL) argument
105 #define ARM_ABSD(p,dreg,sreg) ARM_ABSD_COND(p,dreg,sreg,ARMCOND_AL) argument
109 #define ARM_ABSS(p,dreg,sreg) ARM_ABSS_COND(p,dreg,sreg,ARMCOND_AL) argument
119 #define ARM_NEGD(p,dreg,sreg) ARM_NEGD_COND(p,dreg,sreg,ARMCOND_AL) argument
123 #define ARM_NEGS(p,dreg,sreg) ARM_NEGS_COND(p,dreg,sreg,ARMCOND_AL) argument
133 #define ARM_SQRTD(p,dreg,sreg) ARM_SQRTD_COND(p,dreg,sreg,ARMCOND_AL) argument
147 #define ARM_CMPD(p,dreg,sreg) ARM_CMPD_COND(p,dreg,sreg,ARMCOND_AL) argument
151 #define ARM_CMPS(p,dreg,sreg) ARM_CMPS_COND(p,dreg,sreg,ARMCOND_AL) argument
203 #define ARM_CVTD(p,dreg,sreg) ARM_CVTD_COND(p,dreg,sreg,ARMCOND_AL) argument
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/regulator/
H A Dscmi-regulator.c57 return voltage_ops->config_set(sreg->ph, sreg->id, in scmi_reg_enable()
65 return voltage_ops->config_set(sreg->ph, sreg->id, in scmi_reg_disable()
75 ret = voltage_ops->config_get(sreg->ph, sreg->id, &config); in scmi_reg_is_enabled()
159 sreg->id); in scmi_config_linear_regulator_mappings()
176 sreg->desc.n_voltages = delta_uV / sreg->desc.uV_step; in scmi_config_linear_regulator_mappings()
207 vinfo = voltage_ops->info_get(sreg->ph, sreg->id); in scmi_regulator_common_init()
230 sreg->desc.id = sreg->id; in scmi_regulator_common_init()
234 sreg->desc.of_match = sreg->of_node->full_name; in scmi_regulator_common_init()
250 sreg->conf.driver_data = sreg; in scmi_regulator_common_init()
365 if (!sreg) in scmi_regulator_probe()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/regulator/
H A Dscmi-regulator.c57 return voltage_ops->config_set(sreg->ph, sreg->id, in scmi_reg_enable()
65 return voltage_ops->config_set(sreg->ph, sreg->id, in scmi_reg_disable()
75 ret = voltage_ops->config_get(sreg->ph, sreg->id, &config); in scmi_reg_is_enabled()
159 sreg->id); in scmi_config_linear_regulator_mappings()
176 sreg->desc.n_voltages = delta_uV / sreg->desc.uV_step; in scmi_config_linear_regulator_mappings()
207 vinfo = voltage_ops->info_get(sreg->ph, sreg->id); in scmi_regulator_common_init()
230 sreg->desc.id = sreg->id; in scmi_regulator_common_init()
234 sreg->desc.of_match = sreg->of_node->full_name; in scmi_regulator_common_init()
250 sreg->conf.driver_data = sreg; in scmi_regulator_common_init()
365 if (!sreg) in scmi_regulator_probe()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/regulator/
H A Dscmi-regulator.c57 return voltage_ops->config_set(sreg->ph, sreg->id, in scmi_reg_enable()
65 return voltage_ops->config_set(sreg->ph, sreg->id, in scmi_reg_disable()
75 ret = voltage_ops->config_get(sreg->ph, sreg->id, &config); in scmi_reg_is_enabled()
159 sreg->id); in scmi_config_linear_regulator_mappings()
176 sreg->desc.n_voltages = delta_uV / sreg->desc.uV_step; in scmi_config_linear_regulator_mappings()
207 vinfo = voltage_ops->info_get(sreg->ph, sreg->id); in scmi_regulator_common_init()
230 sreg->desc.id = sreg->id; in scmi_regulator_common_init()
234 sreg->desc.of_match = sreg->of_node->full_name; in scmi_regulator_common_init()
250 sreg->conf.driver_data = sreg; in scmi_regulator_common_init()
365 if (!sreg) in scmi_regulator_probe()
[all …]
/dports/emulators/dolphin-emu/dolphin-3152428/Source/Core/Core/DSP/Interpreter/
H A DDSPIntExtOps.cpp75 switch (sreg) in mv()
97 switch (sreg) in s()
120 switch (sreg) in sn()
149 WriteToBackLog(3, sreg, dsp_increment_addr_reg(sreg)); in l()
154 WriteToBackLog(1, sreg, dsp_increment_addr_reg(sreg)); in l()
173 WriteToBackLog(3, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r.ix[sreg])); in ln()
178 WriteToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r.ix[sreg])); in ln()
389 WriteToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r.ix[sreg])); in ldn()
408 WriteToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r.ix[sreg])); in ldaxn()
467 WriteToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r.ix[sreg])); in ldnm()
[all …]
/dports/net-mgmt/netdisco-mibs/netdisco-mibs-4.010/nortel/
H A Dsynro.mib817 sreg-2300x-NMM OBJECT IDENTIFIER ::= { sreg-2300x 1 }
821 sreg-2310x-NMM OBJECT IDENTIFIER ::= { sreg-2310x 1 }
1010 sreg-SMB-BES-GIG OBJECT IDENTIFIER ::= { sreg-SMB-BES 1 }
1020 sreg-SMB-BES-FE OBJECT IDENTIFIER ::= { sreg-SMB-BES 2 }
1043 sreg-SMB-BSR222 OBJECT IDENTIFIER ::= { sreg-SMB-BSR 1 }
1044 sreg-SMB-BSR252 OBJECT IDENTIFIER ::= { sreg-SMB-BSR 2 }
1071 sreg-SMB-BSGX4E OBJECT IDENTIFIER ::= { sreg-SMB-BSG 1 }
1072 sreg-SMB-BSG8EW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 2 }
1073 sreg-SMB-BSG12AW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 3 }
1074 sreg-SMB-BSG12TW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 4 }
[all …]
/dports/net-mgmt/observium/observium/mibs/nortel/
H A DSYNOPTICS-ROOT-MIB817 sreg-2300x-NMM OBJECT IDENTIFIER ::= { sreg-2300x 1 }
821 sreg-2310x-NMM OBJECT IDENTIFIER ::= { sreg-2310x 1 }
1010 sreg-SMB-BES-GIG OBJECT IDENTIFIER ::= { sreg-SMB-BES 1 }
1020 sreg-SMB-BES-FE OBJECT IDENTIFIER ::= { sreg-SMB-BES 2 }
1043 sreg-SMB-BSR222 OBJECT IDENTIFIER ::= { sreg-SMB-BSR 1 }
1044 sreg-SMB-BSR252 OBJECT IDENTIFIER ::= { sreg-SMB-BSR 2 }
1071 sreg-SMB-BSGX4E OBJECT IDENTIFIER ::= { sreg-SMB-BSG 1 }
1072 sreg-SMB-BSG8EW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 2 }
1073 sreg-SMB-BSG12AW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 3 }
1074 sreg-SMB-BSG12TW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 4 }
[all …]
/dports/www/moinmoin/moin-1.9.11/MoinMoin/auth/openidrp_ext/
H A Dopenidrp_sreg.py20 from openid.extensions.sreg import *
38 if sreg and sreg[cfg.openidrp_sreg_username_field] != '':
44 if sreg:
46 if sreg['email'] != '':
47 u.email = sreg['email']
48 if sreg['language'] != '':
49 u.language = sreg['language']
50 if sreg['timezone'] != '':
52 if sreg['fullname'] != '':
80 sreg['language'] = sreg['language'][0:2]
[all …]
/dports/net-mgmt/librenms/librenms-21.5.1/mibs/nortel/
H A DSYNOPTICS-ROOT-MIB758 sreg-2300x-NMM OBJECT IDENTIFIER ::= { sreg-2300x 1 }
762 sreg-2310x-NMM OBJECT IDENTIFIER ::= { sreg-2310x 1 }
951 sreg-SMB-BES-GIG OBJECT IDENTIFIER ::= { sreg-SMB-BES 1 }
961 sreg-SMB-BES-FE OBJECT IDENTIFIER ::= { sreg-SMB-BES 2 }
984 sreg-SMB-BSR222 OBJECT IDENTIFIER ::= { sreg-SMB-BSR 1 }
985 sreg-SMB-BSR252 OBJECT IDENTIFIER ::= { sreg-SMB-BSR 2 }
1012 sreg-SMB-BSGX4E OBJECT IDENTIFIER ::= { sreg-SMB-BSG 1 }
1013 sreg-SMB-BSG8EW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 2 }
1014 sreg-SMB-BSG12AW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 3 }
1015 sreg-SMB-BSG12TW OBJECT IDENTIFIER ::= { sreg-SMB-BSG 4 }
[all …]
/dports/emulators/dolphin-emu/dolphin-3152428/Source/Core/Core/DSP/Jit/x64/
H A DDSPJitExtOps.cpp115 u8 sreg = opc & 0x3; in l() local
140 u8 sreg = opc & 0x3; in ln() local
156 increase_addr_reg(sreg, sreg); in ln()
166 u8 sreg = opc & 0x1; in ls() local
191 u8 sreg = opc & 0x1; in lsn() local
216 u8 sreg = opc & 0x1; in lsm() local
242 u8 sreg = opc & 0x1; in lsnm() local
456 increase_addr_reg(sreg, sreg); in ldn()
487 increase_addr_reg(sreg, sreg); in ldaxn()
582 increase_addr_reg(sreg, sreg); in ldnm()
[all …]
/dports/editors/fpc-ide/fpc-3.2.2/compiler/powerpc64/
H A Dhlcgcpu.pas68 if (sreg.startbit<>0) or
69 (sreg.bitlen<>tcgsize2size[subsetcgsize]*8) then
71 …ncat(taicpu.op_reg_reg_const_const(A_RLDICL,destreg,sreg.subsetreg,(64-sreg.startbit) and 63,64-sr…
73 if (sreg.bitlen mod 8)=0 then
80 cg.a_op_const_reg(list,OP_SHL,OS_INT,64-sreg.bitlen,destreg);
81 cg.a_op_const_reg(list,OP_SAR,OS_INT,64-sreg.bitlen,destreg);
86 … cg.a_load_reg_reg(list,tcgsize2unsigned[sreg.subsetregsize],subsetcgsize,sreg.subsetreg,destreg);
103 a_load_reg_subsetreg(list,tosubsetsize,tosubsetsize,tmpreg,sreg);
114 else if sreg.bitlen<>sizeof(aint)*8 then
116 ….concat(taicpu.op_reg_reg_const_const(A_INSRDI,sreg.subsetreg,fromreg,sreg.bitlen,(64-(sreg.startb…
[all …]
/dports/lang/fpc/fpc-3.2.2/compiler/powerpc64/
H A Dhlcgcpu.pas68 if (sreg.startbit<>0) or
69 (sreg.bitlen<>tcgsize2size[subsetcgsize]*8) then
71 …ncat(taicpu.op_reg_reg_const_const(A_RLDICL,destreg,sreg.subsetreg,(64-sreg.startbit) and 63,64-sr…
73 if (sreg.bitlen mod 8)=0 then
80 cg.a_op_const_reg(list,OP_SHL,OS_INT,64-sreg.bitlen,destreg);
81 cg.a_op_const_reg(list,OP_SAR,OS_INT,64-sreg.bitlen,destreg);
86 … cg.a_load_reg_reg(list,tcgsize2unsigned[sreg.subsetregsize],subsetcgsize,sreg.subsetreg,destreg);
103 a_load_reg_subsetreg(list,tosubsetsize,tosubsetsize,tmpreg,sreg);
114 else if sreg.bitlen<>sizeof(aint)*8 then
116 ….concat(taicpu.op_reg_reg_const_const(A_INSRDI,sreg.subsetreg,fromreg,sreg.bitlen,(64-(sreg.startb…
[all …]
/dports/lang/fpc-source/fpc-3.2.2/compiler/powerpc64/
H A Dhlcgcpu.pas68 if (sreg.startbit<>0) or
69 (sreg.bitlen<>tcgsize2size[subsetcgsize]*8) then
71 …ncat(taicpu.op_reg_reg_const_const(A_RLDICL,destreg,sreg.subsetreg,(64-sreg.startbit) and 63,64-sr…
73 if (sreg.bitlen mod 8)=0 then
80 cg.a_op_const_reg(list,OP_SHL,OS_INT,64-sreg.bitlen,destreg);
81 cg.a_op_const_reg(list,OP_SAR,OS_INT,64-sreg.bitlen,destreg);
86 … cg.a_load_reg_reg(list,tcgsize2unsigned[sreg.subsetregsize],subsetcgsize,sreg.subsetreg,destreg);
103 a_load_reg_subsetreg(list,tosubsetsize,tosubsetsize,tmpreg,sreg);
114 else if sreg.bitlen<>sizeof(aint)*8 then
116 ….concat(taicpu.op_reg_reg_const_const(A_INSRDI,sreg.subsetreg,fromreg,sreg.bitlen,(64-(sreg.startb…
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/NVPTX/
H A Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]

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