| /dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 2788 int DefStageNum = Schedule.stageScheduled(getSUnit(Def)); in updateInstruction()
2891 int StagePhi = Schedule.stageScheduled(getSUnit(Phi)) + PhiNum; in rewriteScheduledInstr()
2911 int StageSched = Schedule.stageScheduled(OrigMISU); in rewriteScheduledInstr()
3018 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
3296 int StageInst1 = stageScheduled(SU); in orderDependence()
3415 int DefStage = stageScheduled(DefSU); in isLoopCarried()
3426 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
3468 int StageDef = stageScheduled(&SU); in isValidSchedule()
3473 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
3644 int DefStage = stageScheduled(I.first); in finalizeSchedule()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 2979 int DefStageNum = Schedule.stageScheduled(getSUnit(Def)); in updateInstruction()
3082 int StagePhi = Schedule.stageScheduled(getSUnit(Phi)) + PhiNum; in rewriteScheduledInstr()
3102 int StageSched = Schedule.stageScheduled(OrigMISU); in rewriteScheduledInstr()
3209 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
3495 int StageInst1 = stageScheduled(SU); in orderDependence()
3622 int DefStage = stageScheduled(DefSU); in isLoopCarried()
3633 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
3675 int StageDef = stageScheduled(&SU); in isValidSchedule()
3680 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
3853 int DefStage = stageScheduled(I.first); in finalizeSchedule()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 656 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
661 int stageScheduled(SUnit *SU) const { in stageScheduled() function in __anon56883db30111::SMSchedule
3394 int StageSched = Schedule.stageScheduled(OrigMISU); in rewriteScheduledInstr()
3501 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
3779 int StageInst1 = stageScheduled(SU); in orderDependence()
3898 int DefStage = stageScheduled(DefSU); in isLoopCarried()
3909 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
3951 int StageDef = stageScheduled(&SU); in isValidSchedule()
3956 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
4127 int DefStage = stageScheduled(I.first); in finalizeSchedule()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 608 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2250 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2252 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2562 int StageInst1 = stageScheduled(SU); in orderDependence()
2581 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2611 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2689 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2700 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2742 int StageDef = stageScheduled(&SU); in isValidSchedule()
2747 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 607 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2248 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2250 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2560 int StageInst1 = stageScheduled(SU); in orderDependence()
2579 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2609 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2687 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2698 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2740 int StageDef = stageScheduled(&SU); in isValidSchedule()
2745 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2162 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2164 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2468 int StageInst1 = stageScheduled(SU); in orderDependence()
2487 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2595 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2606 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2648 int StageDef = stageScheduled(&SU); in isValidSchedule()
2653 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2235 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2237 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2545 int StageInst1 = stageScheduled(SU); in orderDependence()
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2672 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2683 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2724 int StageDef = stageScheduled(&SU); in isValidSchedule()
2729 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2235 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2237 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2545 int StageInst1 = stageScheduled(SU); in orderDependence()
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2672 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2683 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2724 int StageDef = stageScheduled(&SU); in isValidSchedule()
2729 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 618 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2257 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2259 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2569 int StageInst1 = stageScheduled(SU); in orderDependence()
2588 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2618 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2696 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2707 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2749 int StageDef = stageScheduled(&SU); in isValidSchedule()
2754 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 607 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2248 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2250 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2560 int StageInst1 = stageScheduled(SU); in orderDependence()
2579 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2609 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2687 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2698 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2740 int StageDef = stageScheduled(&SU); in isValidSchedule()
2745 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2162 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2164 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2468 int StageInst1 = stageScheduled(SU); in orderDependence()
2487 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2595 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2606 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2648 int StageDef = stageScheduled(&SU); in isValidSchedule()
2653 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2235 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2237 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2545 int StageInst1 = stageScheduled(SU); in orderDependence()
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2672 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2683 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2724 int StageDef = stageScheduled(&SU); in isValidSchedule()
2729 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 618 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2234 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2236 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2544 int StageInst1 = stageScheduled(SU); in orderDependence()
2563 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2593 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2671 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2682 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2723 int StageDef = stageScheduled(&SU); in isValidSchedule()
2728 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2235 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2237 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2545 int StageInst1 = stageScheduled(SU); in orderDependence()
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2672 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2683 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2724 int StageDef = stageScheduled(&SU); in isValidSchedule()
2729 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 618 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2257 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2259 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2569 int StageInst1 = stageScheduled(SU); in orderDependence()
2588 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2618 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2696 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2707 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2749 int StageDef = stageScheduled(&SU); in isValidSchedule()
2754 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
2162 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2164 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2468 int StageInst1 = stageScheduled(SU); in orderDependence()
2487 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2595 int DefStage = stageScheduled(DefSU); in isLoopCarried()
2606 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
2648 int StageDef = stageScheduled(&SU); in isValidSchedule()
2653 if (stageScheduled(SI.getSUnit()) != StageDef) in isValidSchedule()
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU);
2235 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef));
2237 int BaseStageNum = Schedule.stageScheduled(SU);
2545 int StageInst1 = stageScheduled(SU);
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 &&
2672 int DefStage = stageScheduled(DefSU);
2683 int LoopStage = stageScheduled(UseSU);
2724 int StageDef = stageScheduled(&SU);
2729 if (stageScheduled(SI.getSUnit()) != StageDef)
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 558 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
563 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 564 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
569 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/devel/llvm10/llvm-10.0.1.src/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 549 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
554 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 558 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
563 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 555 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
560 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/devel/llvm11/llvm-11.0.1.src/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 564 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
569 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 549 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
554 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 558 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
563 int stageScheduled(SUnit *SU) const { in stageScheduled() function
|