Searched refs:stage_shreg (Results 1 – 1 of 1) sorted by relevance
169 reg [SHREG_WIDTH-1:0] stage_shreg[0:LATENCY-1]; register175 assign o_tlast_fifo = stage_shreg[LATENCY-1][SHREG_TLAST_LOC];176 assign o_tkeep_fifo = stage_shreg[LATENCY-1][SHREG_TKEEP_HI:SHREG_TKEEP_LO];177 …assign o_tdata_fifo = SIDEBAND_DATAPATH[0] ? s_sideband_data : stage_shreg[LATENCY-1][(WIDTH*NSPC…182 stage_shreg[i] <= {SHREG_WIDTH{1'b0}};187 stage_shreg[i] <= {SHREG_WIDTH{1'b0}};190 stage_shreg[i] <= (i == 0) ? shreg_input : stage_shreg[i-1];196 … assign stage_eop[i] = stage_stb[i] & ((i == 0) ? i_tlast : stage_shreg[i-1][SHREG_TLAST_LOC]);