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Searched refs:status_rxdfifo_udflow_tog (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/
H A Drx_dequeue.v44 pkt_rx_err, pkt_rx_mod, pkt_rx_avail, status_rxdfifo_udflow_tog,
70 output status_rxdfifo_udflow_tog; port
81 reg status_rxdfifo_udflow_tog; register
111 status_rxdfifo_udflow_tog <= 1'b0;
199 status_rxdfifo_udflow_tog <= ~status_rxdfifo_udflow_tog;
H A Dsync_clk_wb.v49 status_rxdfifo_ovflow_tog, status_rxdfifo_udflow_tog,
66 input status_rxdfifo_udflow_tog; port
119 status_rxdfifo_udflow_tog,
H A Dxge_mac_wb.v117 wire status_rxdfifo_udflow_tog;// From rx_dq0 of rx_dequeue.v net
159 .status_rxdfifo_udflow (status_rxdfifo_udflow_tog),
184 .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
H A Dxge_mac.v180 .status_rxdfifo_udflow_tog(status_rxdfifo_udflow),