Searched refs:status_txdfifo_ovflow (Results 1 – 9 of 9) sorted by relevance
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/ |
H A D | xge_mac_wb.v | 118 wire status_txdfifo_ovflow; // From sync_clk_wb0 of sync_clk_wb.v net 156 .status_txdfifo_ovflow (status_txdfifo_ovflow_tog), 169 .status_txdfifo_ovflow (status_txdfifo_ovflow), 213 .status_txdfifo_ovflow (status_txdfifo_ovflow),
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H A D | sync_clk_wb.v | 43 status_crc_error, status_fragment_error, status_txdfifo_ovflow, 76 output status_txdfifo_ovflow; port 98 assign status_txdfifo_ovflow = sig_out1[4];
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H A D | xge_mac.v | 44 status_crc_error, status_fragment_error, status_txdfifo_ovflow, 88 output status_txdfifo_ovflow; port 227 .status_txdfifo_ovflow_tog(status_txdfifo_ovflow),
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H A D | wishbone_if.v | 47 status_crc_error, status_fragment_error, status_txdfifo_ovflow, 70 input status_txdfifo_ovflow; port 250 status_txdfifo_ovflow
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge_interface/ |
H A D | xge_mac_wrapper.v | 58 output status_txdfifo_ovflow, port 181 assign status_txdfifo_ovflow = 1'b0; 223 .status_txdfifo_ovflow (status_txdfifo_ovflow),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ |
H A D | ten_gig_eth_loopback_tb.sv | 216 .status_txdfifo_ovflow (), 315 .status_txdfifo_ovflow (),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/ |
H A D | arm_to_sfp_tb.sv | 203 .status_txdfifo_ovflow (), 316 .status_txdfifo_ovflow (),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
H A D | n3xx_mgt_io_core.v | 341 .status_txdfifo_ovflow(mac_status[2]),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
H A D | n3xx_mgt_io_core.v | 394 .status_txdfifo_ovflow(mac_status[2]),
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