Home
last modified time | relevance | path

Searched refs:status_txdfifo_ovflow (Results 1 – 9 of 9) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/
H A Dxge_mac_wb.v118 wire status_txdfifo_ovflow; // From sync_clk_wb0 of sync_clk_wb.v net
156 .status_txdfifo_ovflow (status_txdfifo_ovflow_tog),
169 .status_txdfifo_ovflow (status_txdfifo_ovflow),
213 .status_txdfifo_ovflow (status_txdfifo_ovflow),
H A Dsync_clk_wb.v43 status_crc_error, status_fragment_error, status_txdfifo_ovflow,
76 output status_txdfifo_ovflow; port
98 assign status_txdfifo_ovflow = sig_out1[4];
H A Dxge_mac.v44 status_crc_error, status_fragment_error, status_txdfifo_ovflow,
88 output status_txdfifo_ovflow; port
227 .status_txdfifo_ovflow_tog(status_txdfifo_ovflow),
H A Dwishbone_if.v47 status_crc_error, status_fragment_error, status_txdfifo_ovflow,
70 input status_txdfifo_ovflow; port
250 status_txdfifo_ovflow
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge_interface/
H A Dxge_mac_wrapper.v58 output status_txdfifo_ovflow, port
181 assign status_txdfifo_ovflow = 1'b0;
223 .status_txdfifo_ovflow (status_txdfifo_ovflow),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/
H A Dten_gig_eth_loopback_tb.sv216 .status_txdfifo_ovflow (),
315 .status_txdfifo_ovflow (),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/
H A Darm_to_sfp_tb.sv203 .status_txdfifo_ovflow (),
316 .status_txdfifo_ovflow (),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dn3xx_mgt_io_core.v341 .status_txdfifo_ovflow(mac_status[2]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_mgt_io_core.v394 .status_txdfifo_ovflow(mac_status[2]),