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Searched refs:status_txdfifo_ovflow_tog (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/
H A Dtx_enqueue.v44 status_txdfifo_ovflow_tog,
72 output status_txdfifo_ovflow_tog; port
76 reg status_txdfifo_ovflow_tog; register
104 status_txdfifo_ovflow_tog <= 1'b0;
115 status_txdfifo_ovflow_tog <= ~status_txdfifo_ovflow_tog;
H A Dsync_clk_wb.v48 status_txdfifo_ovflow_tog, status_txdfifo_udflow_tog,
60 input status_txdfifo_ovflow_tog; port
116 status_txdfifo_ovflow_tog,
H A Dxge_mac_wb.v119 wire status_txdfifo_ovflow_tog;// From tx_eq0 of tx_enqueue.v net
156 .status_txdfifo_ovflow (status_txdfifo_ovflow_tog),
181 .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog),
H A Dxge_mac.v227 .status_txdfifo_ovflow_tog(status_txdfifo_ovflow),