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Searched refs:sub_wire1 (Results 1 – 8 of 8) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/
H A Dfifo_1kx16.v60 wire sub_wire1; net
65 wire empty = sub_wire1;
77 .empty (sub_wire1),
H A Dfifo_4kx16_dc.v62 wire [11:0] sub_wire1; net
67 wire [11:0] wrusedw = sub_wire1[11:0];
80 .wrusedw (sub_wire1),
H A Dfifo_4k_18.v65 wire [11:0] sub_wire1; net
70 wire [11:0] wrusedw = sub_wire1[11:0];
83 .wrusedw (sub_wire1),
H A Dclk_doubler.v51 wire [0:0] sub_wire1 = sub_wire0[0:0]; net
52 wire c0 = sub_wire1;
H A Dpll.v51 wire [0:0] sub_wire1 = sub_wire0[0:0]; net
52 wire c0 = sub_wire1;
H A Ddspclkpll.v54 wire [0:0] sub_wire1 = sub_wire0[0:0]; net
55 wire c0 = sub_wire1;
H A Dfifo_2k.v3245 wire [10:0] sub_wire1; net
3250 wire [10:0] wrusedw = sub_wire1[10:0];
3263 .wrusedw (sub_wire1),
H A Dfifo_4k.v3397 wire [11:0] sub_wire1; net
3402 wire [11:0] wrusedw = sub_wire1[11:0];
3415 .wrusedw (sub_wire1),