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Searched refs:sub_wire4 (Results 1 – 8 of 8) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/
H A Dfifo_1kx16.v63 wire sub_wire4; net
68 wire full = sub_wire4;
80 .full (sub_wire4)
H A Dfifo_4kx16_dc.v65 wire [11:0] sub_wire4; net
70 wire [11:0] rdusedw = sub_wire4[11:0];
83 .rdusedw (sub_wire4)
H A Dfifo_4k_18.v68 wire [11:0] sub_wire4; net
73 wire [11:0] rdusedw = sub_wire4[11:0];
86 .rdusedw (sub_wire4)
H A Dclk_doubler.v50 wire [0:0] sub_wire4 = 1'h0; net
54 wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
H A Dpll.v50 wire [0:0] sub_wire4 = 1'h0; net
54 wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
H A Ddspclkpll.v58 wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; net
61 .inclk (sub_wire4),
H A Dfifo_2k.v3248 wire [10:0] sub_wire4; net
3253 wire [10:0] rdusedw = sub_wire4[10:0];
3266 .rdusedw (sub_wire4));
H A Dfifo_4k.v3400 wire [11:0] sub_wire4; net
3405 wire [11:0] rdusedw = sub_wire4[11:0];
3418 .rdusedw (sub_wire4));