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Searched refs:subopc_imm (Results 1 – 6 of 6) sorted by relevance

/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/VEX/priv/
H A Dhost_amd64_defs.c2625 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
2628 subopc_imm = 2; opc_imma = 0x15; break; in emit_AMD64Instr()
2630 subopc_imm = 0; opc_imma = 0x05; break; in emit_AMD64Instr()
2707 opc = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
2709 case Aalu_CMP: opc = 0x39; subopc_imm = 7; break; in emit_AMD64Instr()
2793 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
3914 subopc_imm = 0; // invalid in emit_AMD64Instr()
3929 limit = 15; opc = 0x73; subopc_imm = 7; in emit_AMD64Instr()
3934 limit = 15; opc = 0x73; subopc_imm = 3; in emit_AMD64Instr()
3941 vassert(limit > 0 && opc > 0 && subopc_imm > 0); in emit_AMD64Instr()
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H A Dhost_x86_defs.c2198 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_X86Instr()
2201 subopc_imm = 2; opc_imma = 0x15; break; in emit_X86Instr()
2270 opc = subopc_imm = opc_imma = 0; in emit_X86Instr()
2272 case Xalu_ADD: opc = 0x01; subopc_imm = 0; break; in emit_X86Instr()
2273 case Xalu_SUB: opc = 0x29; subopc_imm = 5; break; in emit_X86Instr()
2274 case Xalu_CMP: opc = 0x39; subopc_imm = 7; break; in emit_X86Instr()
2952 case 8: opc = 0xDF; subopc_imm = 5; break; in emit_X86Instr()
2953 case 4: opc = 0xDB; subopc_imm = 0; break; in emit_X86Instr()
2967 case 8: opc = 0xDF; subopc_imm = 7; break; in emit_X86Instr()
2968 case 4: opc = 0xDB; subopc_imm = 3; break; in emit_X86Instr()
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/VEX/priv/
H A Dhost_amd64_defs.c2625 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
2628 subopc_imm = 2; opc_imma = 0x15; break; in emit_AMD64Instr()
2630 subopc_imm = 0; opc_imma = 0x05; break; in emit_AMD64Instr()
2707 opc = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
2709 case Aalu_CMP: opc = 0x39; subopc_imm = 7; break; in emit_AMD64Instr()
2793 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
3914 subopc_imm = 0; // invalid in emit_AMD64Instr()
3929 limit = 15; opc = 0x73; subopc_imm = 7; in emit_AMD64Instr()
3934 limit = 15; opc = 0x73; subopc_imm = 3; in emit_AMD64Instr()
3941 vassert(limit > 0 && opc > 0 && subopc_imm > 0); in emit_AMD64Instr()
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H A Dhost_x86_defs.c2198 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_X86Instr()
2201 subopc_imm = 2; opc_imma = 0x15; break; in emit_X86Instr()
2270 opc = subopc_imm = opc_imma = 0; in emit_X86Instr()
2272 case Xalu_ADD: opc = 0x01; subopc_imm = 0; break; in emit_X86Instr()
2273 case Xalu_SUB: opc = 0x29; subopc_imm = 5; break; in emit_X86Instr()
2274 case Xalu_CMP: opc = 0x39; subopc_imm = 7; break; in emit_X86Instr()
2952 case 8: opc = 0xDF; subopc_imm = 5; break; in emit_X86Instr()
2953 case 4: opc = 0xDB; subopc_imm = 0; break; in emit_X86Instr()
2967 case 8: opc = 0xDF; subopc_imm = 7; break; in emit_X86Instr()
2968 case 4: opc = 0xDB; subopc_imm = 3; break; in emit_X86Instr()
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/dports/security/py-pyvex/pyvex-9.0.5405/vex/priv/
H A Dhost_x86_defs.c2198 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_X86Instr()
2201 subopc_imm = 2; opc_imma = 0x15; break; in emit_X86Instr()
2270 opc = subopc_imm = opc_imma = 0; in emit_X86Instr()
2272 case Xalu_ADD: opc = 0x01; subopc_imm = 0; break; in emit_X86Instr()
2273 case Xalu_SUB: opc = 0x29; subopc_imm = 5; break; in emit_X86Instr()
2274 case Xalu_CMP: opc = 0x39; subopc_imm = 7; break; in emit_X86Instr()
2952 case 8: opc = 0xDF; subopc_imm = 5; break; in emit_X86Instr()
2953 case 4: opc = 0xDB; subopc_imm = 0; break; in emit_X86Instr()
2967 case 8: opc = 0xDF; subopc_imm = 7; break; in emit_X86Instr()
2968 case 4: opc = 0xDB; subopc_imm = 3; break; in emit_X86Instr()
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H A Dhost_amd64_defs.c2526 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
2529 subopc_imm = 2; opc_imma = 0x15; break; in emit_AMD64Instr()
2531 subopc_imm = 0; opc_imma = 0x05; break; in emit_AMD64Instr()
2533 subopc_imm = 5; opc_imma = 0x2D; break; in emit_AMD64Instr()
2535 subopc_imm = 3; opc_imma = 0x1D; break; in emit_AMD64Instr()
2537 subopc_imm = 4; opc_imma = 0x25; break; in emit_AMD64Instr()
2539 subopc_imm = 6; opc_imma = 0x35; break; in emit_AMD64Instr()
2541 subopc_imm = 1; opc_imma = 0x0D; break; in emit_AMD64Instr()
2543 subopc_imm = 7; opc_imma = 0x3D; break; in emit_AMD64Instr()
2661 opc = opc_rr = subopc_imm = opc_imma = 0; in emit_AMD64Instr()
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