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Searched refs:sunxi_mctl_com_reg (Results 1 – 25 of 986) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c89 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
90 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
111 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
112 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
136 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
137 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()
163 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
336 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
421 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c89 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
90 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
111 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
112 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
136 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
137 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()
163 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
336 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
421 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c89 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
90 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
111 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
112 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
136 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
137 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()
163 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
336 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
421 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c89 struct sunxi_mctl_com_reg * const mctl_com =
90 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
111 struct sunxi_mctl_com_reg * const mctl_com =
112 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
136 struct sunxi_mctl_com_reg * const mctl_com =
137 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
163 struct sunxi_mctl_com_reg * const mctl_com =
191 struct sunxi_mctl_com_reg * const mctl_com =
336 struct sunxi_mctl_com_reg * const mctl_com =
421 struct sunxi_mctl_com_reg * const mctl_com =
[all …]
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c92 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
93 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
114 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
115 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
139 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
140 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()
166 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
194 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
339 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
424 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c89 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
90 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
111 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
112 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
136 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
137 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()
163 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
336 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
421 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c94 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port()
95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
116 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
141 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_v3s()
164 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64()
191 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h5()
219 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_r40()
389 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr()
480 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init()
[all …]

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