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Searched refs:tCK (Results 1 – 25 of 150) sorted by relevance

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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/
H A DMemInfo.h67 UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds. member
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/
H A DMemInfo.h68 UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds. member
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c433 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
435 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c433 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
435 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c433 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
435 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c433 const u32 tCK = 1000000 / CONFIG_DRAM_CLK;
435 if ((para->cl_cwl_table[i].tCKmin <= tCK) &&
436 (tCK < para->cl_cwl_table[i].tCKmax)) {
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Ddram_sun9i.c435 const u32 tCK = 1000000 / CONFIG_DRAM_CLK; in mctl_channel_init() local
437 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()

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