| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 92 u32 tCKmax; /* in ps */ member
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
861 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
862 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
863 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
864 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 92 u32 tCKmax; /* in ps */ member
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
861 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
862 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
863 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
864 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 92 u32 tCKmax; /* in ps */ member
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
861 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
862 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
863 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
864 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 92 u32 tCKmax; /* in ps */
436 (tCK < para->cl_cwl_table[i].tCKmax)) {
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 },
861 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 },
862 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 },
863 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 },
864 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 }
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 94 u32 tCKmax; /* in ps */ member
438 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
862 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
863 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
864 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
865 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
866 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()
|