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Searched refs:tcg_gen_setcondi_i64 (Results 1 – 25 of 108) sorted by relevance

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/dports/emulators/qemu/qemu-6.2.0/target/mips/tcg/
H A Dmsa_translate.c218 tcg_gen_setcondi_i64(cond, t0, t0, 0); in gen_check_zero_element()
238 tcg_gen_setcondi_i64(cond, t0, t0, 0); in gen_msa_BxZ_V()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/
H A Dtcg-op.h503 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1011 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu/qemu-6.2.0/target/ppc/translate/
H A Dfixedpoint-impl.c.inc431 tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1060 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu/qemu-6.2.0/include/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1056 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu60/qemu-6.0.0/include/tcg/
H A Dtcg-op.h510 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1052 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu5/qemu-5.2.0/include/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1065 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu42/qemu-4.2.1/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1060 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1060 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1056 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/tcg/
H A Dmsa_translate.c347 tcg_gen_setcondi_i64(cond, t0, t0, 0);
365 tcg_gen_setcondi_i64(cond, t0, t0, 0);
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/tcg/
H A Dtcg-op.h513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1091 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dmsa_translate.c348 tcg_gen_setcondi_i64(cond, t0, t0, 0); in gen_check_zero_element()
366 tcg_gen_setcondi_i64(cond, t0, t0, 0); in gen_msa_BxZ_V()
/dports/emulators/qemu-utils/qemu-4.2.1/target/tricore/
H A Dtranslate.c549 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
551 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1118 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1119 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1365 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1367 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1974 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1981 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1982 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2181 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu5/qemu-5.2.0/target/tricore/
H A Dtranslate.c554 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
556 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1123 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1124 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1370 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1372 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1979 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1986 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1987 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2186 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/tricore/
H A Dtranslate.c549 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
551 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1118 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1119 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1365 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1367 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1974 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1981 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1982 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2181 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu42/qemu-4.2.1/target/tricore/
H A Dtranslate.c549 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
551 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1118 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1119 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1365 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1367 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1974 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1981 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1982 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2181 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/tricore/
H A Dtranslate.c557 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
559 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1126 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1127 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1373 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1375 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1982 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1989 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1990 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2189 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/tricore/
H A Dtranslate.c549 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
551 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1118 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1119 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1365 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1367 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1974 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1981 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1982 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2181 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/tricore/
H A Dtranslate.c554 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
556 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1123 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1124 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1370 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1372 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1979 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1986 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1987 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2186 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu/qemu-6.2.0/target/tricore/
H A Dtranslate.c554 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
556 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1123 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1124 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1370 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1372 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1979 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1986 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1987 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2186 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu60/qemu-6.0.0/target/tricore/
H A Dtranslate.c554 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
556 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1123 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1124 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1370 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1372 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1979 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1986 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1987 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2186 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
/dports/emulators/qemu-utils/qemu-4.2.1/target/ppc/
H A Dtranslate.c1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_divd()
1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divd()
1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divd()
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divd()
1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_modd()
1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modd()
1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_modd()
/dports/emulators/qemu5/qemu-5.2.0/target/ppc/
H A Dtranslate.c1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_divd()
1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divd()
1082 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divd()
1088 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divd()
1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_modd()
1189 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modd()
1191 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_modd()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/ppc/
H A Dtranslate.c1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_divd()
1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divd()
1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divd()
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divd()
1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_modd()
1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modd()
1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_modd()

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