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Searched refs:tx_tlast (Results 1 – 21 of 21) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/
H A Daxi_stream_to_wb.v46 output tx_tlast, port
227 if (tx_tlast) begin
246 assign tx_tuser = (tx_tlast)? {tx_error, tx_bytes[2:0]} : 4'b0;
249 assign tx_tlast = (tx_counter == tx_bytes[AWIDTH-1:3]);
262 tx_state, tx_tlast, tx_tvalid, tx_tready, tx_tuser[2:0], //8
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/
H A Db205.v209 wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast; net
253 .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
290 .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
H A Db205_core.v31 input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, port
242 .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/
H A Dfifo64_to_axi4lite.v49 wire tx_tlast; net
64 .i_tlast(tx_tlast),
129 .axi_str_txd_tlast(tx_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/
H A Db200.v244 wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast; net
287 .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
352 .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
H A Db200_core.v33 input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, port
278 .i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready),
317 ….tx_tdata(r0_tx_tdata), .tx_tlast(r0_tx_tlast), .tx_tvalid(r0_tx_tvalid), .tx_tready(r0_tx_tready),
349 ….tx_tdata(r1_tx_tdata), .tx_tlast(r1_tx_tlast), .tx_tvalid(r1_tx_tvalid), .tx_tready(r1_tx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge_interface/
H A Dxge_mac_wrapper.v50 input tx_tlast, port
353 .s_axis_tlast(tx_tlast),
368 assign tx_tlast_int = tx_tlast;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/simple_gemac/
H A Dgmii_to_axis.v39 input tx_tlast, port
196 .s_axis_tlast(tx_tlast),
H A Dsimple_gemac_wrapper.v21 input [63:0] tx_tdata, input [3:0] tx_tuser, input tx_tlast, input tx_tvalid, output tx_tready, port
126 .s_axis_tdata(tx_tdata), .s_axis_tlast(tx_tlast), .s_axis_tuser(tx_tuser),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/
H A Dten_gig_eth_loopback_tb.sv208 .tx_tlast(m_tx_chdr.axis.tlast),
307 .tx_tlast(loop_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/
H A Done_gig_eth_loopback_tb.sv177 .tx_tlast(m_tx_chdr.axis.tlast),
240 .tx_tlast(loop_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/gpif2/
H A Dgpif2_slave_fifo32.v44 output [63:0] tx_tdata, output tx_tlast, output tx_tvalid, input tx_tready, port
487 .o_tdata(tx_tdata), .o_tlast(tx_tlast), .o_tvalid(tx_tvalid), .o_tready(tx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dsoft_ctrl.v70 output tx_tlast, port
276 ….o_aclk(clk), .o_tdata({tx_tdata, tx_tuser, tx_tlast}), .o_tvalid(tx_tvalid), .o_tready(tx_tready)…
291 .tx_tdata(tx_tdata_div2), .tx_tuser(tx_tuser_div2), .tx_tlast(tx_tlast_div2),
H A Dx300_sfpp_io_core.v181 .tx_tlast(c2mac_tlast),
260 .tx_tlast(c2mac_tlast),
H A Dbus_int.v294 .tx_tlast(zpuo_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/
H A Darm_to_sfp_tb.sv195 .tx_tlast(c2e_tlast),
308 .tx_tlast(loop_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dn3xx_mgt_io_core.v333 .tx_tlast(c2mac_tlast),
432 .tx_tlast(c2mac_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_mgt_io_core.v386 .tx_tlast(c2mac_tlast),
523 .tx_tlast(c2mac_tlast),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/radio_200/
H A Dradio_legacy.v29 input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, port
96 .i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/
H A Db200.edf25346 (net tx_tlast (joined
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/planahead/planahead.data/cache/
H A Db200_ngc_d1c0f267.edif30294 (net tx_tlast