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Searched refs:uictr (Results 1 – 12 of 12) sorted by relevance

/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Dppc-uic.c123 if (uic->uictr & mask) { in ppcuic_set_irq()
167 ret = uic->uictr; in dcr_read_uic()
222 uic->uictr = val; in dcr_write_uic()
244 uic->uictr = 0x00000000; in ppc_uic_reset()
292 VMSTATE_UINT32(uictr, PPCUIC),
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Dppc-uic.c123 if (uic->uictr & mask) { in ppcuic_set_irq()
167 ret = uic->uictr; in dcr_read_uic()
222 uic->uictr = val; in dcr_write_uic()
244 uic->uictr = 0x00000000; in ppc_uic_reset()
292 VMSTATE_UINT32(uictr, PPCUIC),
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Dppc-uic.c123 if (uic->uictr & mask) { in ppcuic_set_irq()
167 ret = uic->uictr; in dcr_read_uic()
222 uic->uictr = val; in dcr_write_uic()
244 uic->uictr = 0x00000000; in ppc_uic_reset()
292 VMSTATE_UINT32(uictr, PPCUIC),
/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/
H A Dppc-uic.h75 uint32_t uictr; /* Triggering register */ member
/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/
H A Dppc-uic.h75 uint32_t uictr; /* Triggering register */ member
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/intc/
H A Dppc-uic.h75 uint32_t uictr; /* Triggering register */ member
/dports/emulators/qemu42/qemu-4.2.1/hw/ppc/
H A Dppc4xx_devs.c102 uint32_t uictr; /* Triggering register */ member
175 if (uic->uictr & mask) { in ppcuic_set_irq()
217 ret = uic->uictr; in dcr_read_uic()
270 uic->uictr = val; in dcr_write_uic()
293 uic->uictr = 0x00000000; in ppcuic_reset()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/ppc/
H A Dppc4xx_devs.c102 uint32_t uictr; /* Triggering register */ member
175 if (uic->uictr & mask) { in ppcuic_set_irq()
217 ret = uic->uictr; in dcr_read_uic()
270 uic->uictr = val; in dcr_write_uic()
293 uic->uictr = 0x00000000; in ppcuic_reset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/ppc/
H A Dppc4xx_devs.c102 uint32_t uictr; /* Triggering register */ member
175 if (uic->uictr & mask) { in ppcuic_set_irq()
217 ret = uic->uictr; in dcr_read_uic()
270 uic->uictr = val; in dcr_write_uic()
293 uic->uictr = 0x00000000; in ppcuic_reset()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/ppc/
H A Dppc4xx_devs.c102 uint32_t uictr; /* Triggering register */ member
175 if (uic->uictr & mask) { in ppcuic_set_irq()
217 ret = uic->uictr; in dcr_read_uic()
270 uic->uictr = val; in dcr_write_uic()
293 uic->uictr = 0x00000000; in ppcuic_reset()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/ppc/
H A Dppc4xx_devs.c101 uint32_t uictr; /* Triggering register */ member
174 if (uic->uictr & mask) { in ppcuic_set_irq()
216 ret = uic->uictr; in dcr_read_uic()
269 uic->uictr = val; in dcr_write_uic()
292 uic->uictr = 0x00000000; in ppcuic_reset()
/dports/emulators/qemu5/qemu-5.2.0/hw/ppc/
H A Dppc4xx_devs.c102 uint32_t uictr; /* Triggering register */ member
175 if (uic->uictr & mask) { in ppcuic_set_irq()
217 ret = uic->uictr; in dcr_read_uic()
270 uic->uictr = val; in dcr_write_uic()
293 uic->uictr = 0x00000000; in ppcuic_reset()