Searched refs:undef_b (Results 1 – 4 of 4) sorted by relevance
/dports/cad/yosys/yosys-yosys-0.12/kernel/ |
H A D | satgen.cc | 36 extendSignalWidth(undef_a, undef_b, cell, true); in importCell() 41 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); in importCell() 169 int b0 = ez->AND(ez->NOT(b), ez->NOT(undef_b)); in importCell() 186 int b1 = ez->AND(b, ez->NOT(undef_b)); in importCell() 286 std::vector<int> part_of_undef_b(undef_b.begin()+i*a.size(), undef_b.begin()+(i+1)*a.size()); in importCell() 416 int bX = ez->expression(ezSAT::OpOr, undef_b); in importCell() 446 extendSignalWidth(undef_a, undef_b, cell, true); in importCell() 448 b = ez->vec_or(b, undef_b); in importCell() 471 extendSignalWidth(undef_a, undef_b, cell, true); in importCell() 488 extendSignalWidth(undef_a, undef_b, cell, true); in importCell() [all …]
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H A D | satgen.h | 265 … &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) { in mux() 271 std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); in mux() 272 undef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a)); in mux()
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/dports/cad/yosys/yosys-yosys-0.12/passes/opt/ |
H A D | opt_expr.cc | 233 SigSpec undef_a, undef_y, undef_b; in group_cell_inputs() local 240 undef_b.append(State::S0); in group_cell_inputs() 243 undef_b.append(State::S1); in group_cell_inputs() 250 undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]); in group_cell_inputs() 252 undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit()); in group_cell_inputs() 263 …log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_s… in group_cell_inputs() 264 module->connect(undef_y, undef_b); in group_cell_inputs()
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/dports/lang/onyx/onyx-5.1.2/bin/onyx/ |
H A D | Cookfile.inc.in | 351 tuck_c.nx.in type_a.nx.in type_b.nx.in undef_a.nx.in undef_b.nx.in
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