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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/MC/AMDGPU/
H A Ddl-insts.s138 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
146 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
148 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
150 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
152 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
154 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
156 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
158 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
162 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
172 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/MC/AMDGPU/
H A Ddl-insts.s138 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
146 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
148 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
150 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
152 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
154 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
156 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
158 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
162 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
172 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Ddl-insts.s139 v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
147 v_fmac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
149 v_fmac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
151 v_fmac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
153 v_fmac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
155 v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0 label
157 v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0 label
159 v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0 label
163 v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0 label
173 v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/llvm10/llvm-10.0.1.src/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/graphics/llvm-mesa/llvm-13.0.1.src/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/llvm11/llvm-11.0.1.src/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`vsrc0<amdgpu_synid…
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst44 …v_fmac_f32_dpp :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`vsrc0<amdgpu_synid…

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